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283 lines
8.3 KiB
Diff
283 lines
8.3 KiB
Diff
From ea6871c5b3a934d0bfe08082e95c3b952f93ef39 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Fri, 18 Jul 2014 15:48:35 -0300
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Subject: [PATCH] clk: sunxi: PLL2 support for sun4i, sun5i and sun7i
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This patch adds support for PLL2 and derivates on A10 revision B and
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higher, as well as on sun5i and sun7i SoCs. As this PLL is only used for
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audio and requires good accuracy, we only support two known good rates.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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drivers/clk/sunxi/Makefile | 1 +
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drivers/clk/sunxi/clk-a10-pll2.c | 249 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 250 insertions(+)
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create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c
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--- a/drivers/clk/sunxi/Makefile
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+++ b/drivers/clk/sunxi/Makefile
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@@ -4,6 +4,7 @@
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-hosc.o
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+obj-y += clk-a10-pll2.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-sun8i-mbus.o
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--- /dev/null
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+++ b/drivers/clk/sunxi/clk-a10-pll2.c
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@@ -0,0 +1,249 @@
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+/*
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+ * Copyright 2013 Emilio López
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+ *
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+ * Emilio López <emilio@elopez.com.ar>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/slab.h>
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+
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+#define SUN4I_PLL2_ENABLE 31
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+#define SUN4I_PLL2_POST_DIV 26
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+#define SUN4I_PLL2_POST_DIV_MASK 0xF
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+#define SUN4I_PLL2_N 8
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+#define SUN4I_PLL2_N_MASK 0x7F
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+#define SUN4I_PLL2_PRE_DIV 0
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+#define SUN4I_PLL2_PRE_DIV_MASK 0x1F
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+
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+#define SUN4I_PLL2_OUTPUTS 4
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+
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+struct sun4i_pll2_clk {
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+ struct clk_hw hw;
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+ void __iomem *reg;
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+};
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+
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+static inline struct sun4i_pll2_clk *to_sun4i_pll2_clk(struct clk_hw *hw)
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+{
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+ return container_of(hw, struct sun4i_pll2_clk, hw);
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+}
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+
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+static unsigned long sun4i_pll2_1x_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
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+ int n, prediv, postdiv;
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+
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+ u32 val = readl(clk->reg);
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+ n = (val >> SUN4I_PLL2_N) & SUN4I_PLL2_N_MASK;
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+ prediv = (val >> SUN4I_PLL2_PRE_DIV) & SUN4I_PLL2_PRE_DIV_MASK;
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+ postdiv = (val >> SUN4I_PLL2_POST_DIV) & SUN4I_PLL2_POST_DIV_MASK;
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+
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+ /* 0 is a special case and means 1 */
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+ if (n == 0)
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+ n = 1;
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+ if (prediv == 0)
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+ prediv = 1;
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+ if (postdiv == 0)
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+ postdiv = 1;
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+
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+ return ((parent_rate * n) / prediv) / postdiv;
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+}
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+
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+static unsigned long sun4i_pll2_8x_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
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+ int n, prediv;
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+
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+ u32 val = readl(clk->reg);
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+ n = (val >> SUN4I_PLL2_N) & SUN4I_PLL2_N_MASK;
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+ prediv = (val >> SUN4I_PLL2_PRE_DIV) & SUN4I_PLL2_PRE_DIV_MASK;
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+
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+ /* 0 is a special case and means 1 */
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+ if (n == 0)
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+ n = 1;
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+ if (prediv == 0)
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+ prediv = 1;
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+
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+ return ((parent_rate * 2 * n) / prediv);
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+}
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+
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+static unsigned long sun4i_pll2_4x_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ return sun4i_pll2_8x_recalc_rate(hw, parent_rate / 2);
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+}
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+
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+static unsigned long sun4i_pll2_2x_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ return sun4i_pll2_8x_recalc_rate(hw, parent_rate / 4);
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+}
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+
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+static long sun4i_pll2_1x_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ /*
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+ * There is only two interesting rates for the audio PLL, the
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+ * rest isn't really usable due to accuracy concerns. Therefore,
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+ * we specifically round to those rates here
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+ */
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+ if (rate < 22579200)
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+ return -EINVAL;
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+
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+ if (rate >= 22579200 && rate < 24576000)
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+ return 22579200;
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+
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+ return 24576000;
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+}
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+
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+static long sun4i_pll2_8x_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ /*
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+ * We should account for the postdiv that we're undoing on PLL2x8,
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+ * which is always 4 in the usable configurations. The division
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+ * by two is done because PLL2x8 also doubles the rate
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+ */
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+ *parent_rate = (rate * 4) / 2;
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+
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+ return rate;
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+}
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+
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+static long sun4i_pll2_4x_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ /* PLL2x4 * 2 = PLL2x8 */
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+ return sun4i_pll2_8x_round_rate(hw, rate * 2, parent_rate);
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+}
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+
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+static long sun4i_pll2_2x_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ /* PLL2x2 * 4 = PLL2x8 */
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+ return sun4i_pll2_8x_round_rate(hw, rate * 4, parent_rate);
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+}
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+
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+static int sun4i_pll2_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw);
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+ u32 val = readl(clk->reg);
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+
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+ val &= ~(SUN4I_PLL2_N_MASK << SUN4I_PLL2_N);
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+ val &= ~(SUN4I_PLL2_PRE_DIV_MASK << SUN4I_PLL2_PRE_DIV);
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+ val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV);
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+
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+ val |= (21 << SUN4I_PLL2_PRE_DIV) | (4 << SUN4I_PLL2_POST_DIV);
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+
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+ if (rate == 22579200)
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+ val |= (79 << SUN4I_PLL2_N);
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+ else if (rate == 24576000)
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+ val |= (86 << SUN4I_PLL2_N);
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+ else
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+ return -EINVAL;
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+
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+ writel(val, clk->reg);
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+
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+ return 0;
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+}
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+
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+static struct clk_ops sun4i_pll2_ops_1x = {
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+ .recalc_rate = sun4i_pll2_1x_recalc_rate,
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+ .round_rate = sun4i_pll2_1x_round_rate,
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+ .set_rate = sun4i_pll2_set_rate,
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+};
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+
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+static struct clk_ops sun4i_pll2_ops_2x = {
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+ .recalc_rate = sun4i_pll2_2x_recalc_rate,
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+ .round_rate = sun4i_pll2_2x_round_rate,
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+};
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+
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+static struct clk_ops sun4i_pll2_ops_4x = {
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+ .recalc_rate = sun4i_pll2_4x_recalc_rate,
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+ .round_rate = sun4i_pll2_4x_round_rate,
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+};
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+
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+static struct clk_ops sun4i_pll2_ops_8x = {
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+ .recalc_rate = sun4i_pll2_8x_recalc_rate,
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+ .round_rate = sun4i_pll2_8x_round_rate,
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+};
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+
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+static void __init sun4i_pll2_setup(struct device_node *np)
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+{
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+ const char *clk_name = np->name, *parent;
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+ struct clk_onecell_data *clk_data;
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+ struct sun4i_pll2_clk *pll2;
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+ struct clk_gate *gate;
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+ struct clk **clks;
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+ void __iomem *reg;
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+
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+ pll2 = kzalloc(sizeof(*pll2), GFP_KERNEL);
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+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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+ clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
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+ if (!pll2 || !gate || !clk_data || !clks)
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+ goto free_mem;
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+
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+ reg = of_iomap(np, 0);
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+ parent = of_clk_get_parent_name(np, 0);
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+ of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
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+
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+ pll2->reg = reg;
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+ gate->reg = reg;
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+ gate->bit_idx = SUN4I_PLL2_ENABLE;
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+
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+ /* PLL2, also known as PLL2x1 */
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+ of_property_read_string_index(np, "clock-output-names", 0, &clk_name);
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+ clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
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+ &pll2->hw, &sun4i_pll2_ops_1x,
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+ &gate->hw, &clk_gate_ops, 0);
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+ WARN_ON(IS_ERR(clks[0]));
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+ parent = clk_name;
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+
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+ /* PLL2x2, 1/4 the rate of PLL2x8 */
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+ of_property_read_string_index(np, "clock-output-names", 1, &clk_name);
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+ clks[1] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
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+ &pll2->hw, &sun4i_pll2_ops_2x,
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+ NULL, NULL, CLK_SET_RATE_PARENT);
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+ WARN_ON(IS_ERR(clks[1]));
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+
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+ /* PLL2x4, 1/2 the rate of PLL2x8 */
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+ of_property_read_string_index(np, "clock-output-names", 2, &clk_name);
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+ clks[2] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
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+ &pll2->hw, &sun4i_pll2_ops_4x,
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+ NULL, NULL, CLK_SET_RATE_PARENT);
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+ WARN_ON(IS_ERR(clks[2]));
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+
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+ /* PLL2x8, double of PLL2 without the post divisor */
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+ of_property_read_string_index(np, "clock-output-names", 3, &clk_name);
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+ clks[3] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL,
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+ &pll2->hw, &sun4i_pll2_ops_8x,
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+ NULL, NULL, CLK_SET_RATE_PARENT);
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+ WARN_ON(IS_ERR(clks[3]));
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+
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+ clk_data->clks = clks;
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+ clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
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+ of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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+
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+ return;
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+
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+free_mem:
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+ kfree(pll2);
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+ kfree(gate);
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+ kfree(clk_data);
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+ kfree(clks);
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+}
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+CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-b-pll2-clk", sun4i_pll2_setup);
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