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715 lines
18 KiB
Diff
715 lines
18 KiB
Diff
Index: linux-2.6.30.9/drivers/spi/Kconfig
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===================================================================
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--- linux-2.6.30.9.orig/drivers/spi/Kconfig 2009-11-24 21:09:23.000000000 +0100
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+++ linux-2.6.30.9/drivers/spi/Kconfig 2009-11-24 21:09:53.000000000 +0100
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@@ -125,6 +125,12 @@
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If unsure, say N.
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+config SPI_EP93XX
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+ tristate "EP93xx SSP SPI master"
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+ depends on SPI_MASTER && ARCH_EP93XX && EXPERIMENTAL
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+ help
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+ This enables the EP93xx SPI master controller.
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+
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config SPI_IMX
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tristate "Freescale iMX SPI controller"
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depends on ARCH_IMX && EXPERIMENTAL
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Index: linux-2.6.30.9/drivers/spi/Makefile
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===================================================================
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--- linux-2.6.30.9.orig/drivers/spi/Makefile 2009-11-24 21:09:23.000000000 +0100
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+++ linux-2.6.30.9/drivers/spi/Makefile 2009-11-24 21:09:53.000000000 +0100
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@@ -16,6 +16,7 @@
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obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
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+obj-$(CONFIG_SPI_EP93XX) += spi_ep93xx.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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Index: linux-2.6.30.9/drivers/spi/spi_ep93xx.c
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-2.6.30.9/drivers/spi/spi_ep93xx.c 2009-11-24 21:21:25.000000000 +0100
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@@ -0,0 +1,680 @@
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+/*
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+ * linux/drivers/spi/spi_ep93xx.c
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+ *
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+ * Copyright (C) 2007 Manfred Gruber <m.gruber@tirol.com>
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+ * Small changes by Peter Ivanov <ivanovp@gmail.com> to support MMC over SPI, 2008
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+ * SIM.ONE changes by Nuccio Raciti Simplemachine <nuccio.raciti@gmail.com>
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+ *
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+ * Based on pxa2xx_spi.c/spi_imx.c and bitbang.c driver
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#include <linux/blkdev.h>
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/err.h>
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+#include <linux/errno.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/interrupt.h>
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+#include <linux/platform_device.h>
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+#include <linux/spinlock.h>
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+#include <linux/workqueue.h>
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+
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+#include <linux/spi/spi.h>
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+
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+#include <mach/hardware.h>
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+#include <mach/ep93xx-regs.h>
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+#include <asm/gpio.h>
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+
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+/* #define SPI_EP93XX_DEBUG */
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+
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+#define DEFINE_SSP_REG(reg, off) \
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+ static inline u32 read_##reg(void *p) \
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+ { return __raw_readl(p + (off)); } \
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+ static inline void write_##reg(u32 v, void *p) \
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+ { __raw_writel(v, p + (off)); }
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+
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+DEFINE_SSP_REG(SSPCR0, 0x00)
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+DEFINE_SSP_REG(SSPCR1, 0x04)
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+DEFINE_SSP_REG(SSPDR, 0x08)
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+DEFINE_SSP_REG(SSPSR, 0x0c)
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+DEFINE_SSP_REG(SSPCPSR, 0x10)
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+DEFINE_SSP_REG(SSPIIR, 0x14)
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+DEFINE_SSP_REG(SSPICR, 0x14)
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+
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+/* Bits in SSPCR0 */
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+#define SSPCR0_DSS_MASK 0x0000000f
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+#define SSPCR0_FRF_MASK 0x00000030
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+#define SSPCR0_FRF_SHIFT 4
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+#define SSPCR0_FRF_MOTOROLA (0 << SSPCR0_FRF_SHIFT)
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+#define SSPCR0_FRF_TI (1 << SSPCR0_FRF_SHIFT)
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+#define SSPCR0_FRF_NI (2 << SSPCR0_FRF_SHIFT)
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+#define SSPCR0_SPO 0x00000040
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+#define SSPCR0_SPH 0x00000080
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+#define SSPCR0_SCR_MASK 0x0000ff00
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+#define SSPCR0_SCR_SHIFT 8
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+
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+/* Bits in SSPCR1 */
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+#define SSPC1_RIE 0x00000001
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+#define SSPC1_TIE 0x00000002
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+#define SSPC1_RORIE 0x00000004
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+#define SSPC1_LBM 0x00000008
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+#define SSPC1_SSE 0x00000010
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+#define SSPC1_MS 0x00000020
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+#define SSPC1_SOD 0x00000040
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+
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+/* Bits in SSPSR */
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+#define SSPSR_TFE 0x00000001 /* TX FIFO is empty */
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+#define SSPSR_TNF 0x00000002 /* TX FIFO is not full */
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+#define SSPSR_RNE 0x00000004 /* RX FIFO is not empty */
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+#define SSPSR_RFF 0x00000008 /* RX FIFO is full */
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+#define SSPSR_BSY 0x00000010 /* SSP is busy */
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+#define SSPSR_MASK 0x0000001F /* SSP is busy */
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+
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+/* Bits in SSPCPSR */
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+#define SSPCPSR_SCR_MASK 0x000000ff
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+
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+/* Bits in SSPIIR */
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+#define SSPIIR_RIS 0x00000001 /* RX FIFO IRQ status */
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+#define SSPIIR_TIS 0x00000002 /* TX FIFO is not full */
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+#define SSPIIR_RORIS 0x00000004 /* RX FIFO is full */
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+
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+#define SPI_SSPCLK 7.4e6
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+#define SPI_SSPCLK_REV_E2 14.8e6 /* only for chip Rev E2 */
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+#define SPI_MAX_SPEED 3.7e6
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+#define SPI_MAX_SPEED_REV_E2 7.4e6 /* only for chip Rev E2 */
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+#define SPI_CPSDVR_DIV_MIN 2
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+#define SPI_CPSDVR_DIV_MAX 254
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+#define SPI_SCR_DIV_MIN 0
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+#define SPI_SCR_DIV_MAX 255
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+#define SPI_DATARATE_OK 0
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+#define SPI_DATARATE_NOK -1
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+
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+struct driver_data {
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+ /* Driver model hookup */
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+ struct platform_device *pdev;
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+
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+ /* SPI framework hookup */
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+ struct spi_master *master;
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+
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+ /* SSP register addresses */
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+ void *ioaddr;
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+
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+ /* SSP irq */
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+ int irq;
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+
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+ struct list_head queue;
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+
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+ /* SSP spinlock */
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+ spinlock_t lock;
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+
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+ struct workqueue_struct *workqueue;
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+ struct work_struct work;
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+
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+ u8 busy;
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+ u8 use_dma;
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+};
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+
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+static unsigned ep93xx_txrx_8(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct driver_data *drv_data;
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+ const u8 *tx = t->tx_buf;
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+ u8 *rx = t->rx_buf;
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+ unsigned count = t->len;
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+ u8 byte;
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+ int busy;
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+
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+ drv_data = spi_master_get_devdata(spi->master);
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+
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_8: t->len %u \n", t->len);
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+#endif
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+
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+ while (likely(count > 0)) {
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+ byte = 0;
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+ if (tx) {
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+ byte = *tx++;
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_8: write 0x%x \n", byte);
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+#endif
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+ }
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+
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+ write_SSPDR(byte, drv_data->ioaddr);
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+ busy = read_SSPSR(drv_data->ioaddr);
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+ while (busy & SSPSR_BSY) {
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+ cpu_relax();
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+ busy = read_SSPSR(drv_data->ioaddr);
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_8: delay. SSPSR: 0x%X\n", busy);
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+#endif
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+ }
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+ byte = read_SSPDR(drv_data->ioaddr);
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+
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+ if (rx) {
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+ *rx++ = byte;
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_8: read 0x%x \n", byte);
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+#endif
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+ }
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+ count -= 1;
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+ }
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+ return t->len - count;
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+}
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+
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+
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+static unsigned ep93xx_txrx_16(struct spi_device *spi, struct spi_transfer *t)
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+{
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+
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+ struct driver_data *drv_data;
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+ const u16 *tx = t->tx_buf;
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+ u16 *rx = t->rx_buf;
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+ unsigned count = t->len;
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+ u16 word;
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+ int busy;
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+
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+ drv_data = spi_master_get_devdata(spi->master);
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+
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_16: t->len %u \n", t->len);
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+#endif
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+ while (likely(count > 0)) {
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+ word = 0;
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+ if (tx) {
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+ word = *tx++;
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_16: write 0x%x \n", word);
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+#endif
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+ }
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+
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+ write_SSPDR(word, drv_data->ioaddr);
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+ busy = read_SSPSR(drv_data->ioaddr);
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+ while (busy & SSPSR_BSY) {
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+ cpu_relax();
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+ busy = read_SSPSR(drv_data->ioaddr);
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_8: delay.\n");
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+#endif
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+ }
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+
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+ word = read_SSPDR(drv_data->ioaddr);
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+
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+ if (rx) {
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+ *rx++ = word;
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "ep93xx_txrx_16: read 0x%x \n", word);
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+#endif
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+ }
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+ count -= 2;
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+ }
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+ return t->len - count;
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+}
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+
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+static u32 spi_data_rate(u32 speed_hz, u32 *div_cpsdvr, u32 *div_scr,
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+ struct driver_data *drv_data, struct spi_device *spi)
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+{
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+ unsigned int spi_sspclk = SPI_SSPCLK;
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+ unsigned int bus_speed_max = SPI_MAX_SPEED;
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+ unsigned int bus_hz_tmp = 0;
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+ u32 div_cpsdvr_tmp;
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+ u32 div_scr_tmp;
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+ u32 rv = SPI_DATARATE_NOK;
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+ int chip_rev;
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+
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+ /* Checking CHIP_ID */
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+ chip_rev = (__raw_readl (EP93XX_SYSCON_CHIP_ID) >> 28) & 0xF;
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+ if (chip_rev == 7)
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+ {
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+ /* Chip version: Rev E2 */
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+ /* This device has double speed SSP clock */
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+ spi_sspclk = SPI_SSPCLK_REV_E2;
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+ bus_speed_max = SPI_MAX_SPEED_REV_E2;
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "Chip Rev E2 detected! This device has double speed SSP clock.\n");
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+#endif
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+ }
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+
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+ *div_cpsdvr = SPI_CPSDVR_DIV_MAX;
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+ *div_scr = SPI_SCR_DIV_MAX;
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+
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+ for (div_cpsdvr_tmp = SPI_CPSDVR_DIV_MIN;
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+ div_cpsdvr_tmp <= SPI_CPSDVR_DIV_MAX && rv; div_cpsdvr_tmp++) {
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+ for (div_scr_tmp = SPI_SCR_DIV_MIN;
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+ div_scr_tmp <= SPI_SCR_DIV_MAX && rv; div_scr_tmp++) {
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+ bus_hz_tmp = spi_sspclk / (div_cpsdvr_tmp * (1 + div_scr_tmp));
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+ if (bus_hz_tmp <= speed_hz && bus_hz_tmp <= bus_speed_max) {
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+ *div_cpsdvr = div_cpsdvr_tmp;
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+ *div_scr = div_scr_tmp;
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+ rv = SPI_DATARATE_OK;
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+ }
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+ }
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+ }
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info(&spi->dev,
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+ "Needed SPI bus frequency: %i Hz\n", speed_hz);
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+ dev_info(&spi->dev,
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+ "Actual SPI bus frequency: %i Hz\n", bus_hz_tmp);
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+#endif
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+ return rv;
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+}
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+
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+/* Supported modes (returns -EINVAL if not supported mode requested) */
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+#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
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+
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+static int ep93xx_spi_setup(struct spi_device *spi)
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+{
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+ struct driver_data *drv_data;
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+ u16 val;
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+ u32 div_scr;
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+ u32 div_cpsdvr;
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+ unsigned int bits = spi->bits_per_word;
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+ unsigned long speed_hz = spi->max_speed_hz;
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+
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+ drv_data = spi_master_get_devdata(spi->master);
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+
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+ /* enable SSP */
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+ write_SSPCR1(SSPC1_SSE, drv_data->ioaddr);
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+ /* Enable SSP and loopback mode (only for testing!) */
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+ /* write_SSPCR1(SSPC1_SSE | SSPC1_LBM, drv_data->ioaddr); */
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+
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+ if (bits == 0)
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+ bits = 8;
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+ if (bits < 4 || bits > 16) {
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+ dev_err(&spi->dev,
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+ "setup invalid bits_per_word %u (4 to 16)\n", bits);
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+ return -EINVAL;
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+ } else {
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+ val = read_SSPCR0(drv_data->ioaddr);
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+ val = val & ~SSPCR0_DSS_MASK ;
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+ val = val | (bits-1);
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+ write_SSPCR0(val, drv_data->ioaddr);
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info (&spi->dev, "Bits per word: %i\n", bits);
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+#endif
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+ }
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+
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+ if (spi->mode & ~MODEBITS) {
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+ dev_err(&spi->dev, "unsupported mode bits: %x\n",
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+ spi->mode & ~MODEBITS);
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+ return -EINVAL;
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+ } else {
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+ val = read_SSPCR0(drv_data->ioaddr);
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+ val = val & ~SSPCR0_SPO;
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+ val = val & ~SSPCR0_SPH;
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+ if (spi->mode & SPI_CPOL)
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+ {
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+ val = val | SSPCR0_SPO;
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+ }
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info (&spi->dev, "Clock polarity (CPOL): %s\n", (spi->mode & SPI_CPHA) ? "1" : "0");
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+#endif
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+ if (spi->mode & SPI_CPHA)
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+ {
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+ val = val | SSPCR0_SPH;
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+ }
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info (&spi->dev, "Clock phase (CPHA): %s\n", (spi->mode & SPI_CPHA) ? "1" : "0");
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+#endif
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+ write_SSPCR0(val, drv_data->ioaddr);
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+ }
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+
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+ if (SPI_DATARATE_OK == (spi_data_rate(speed_hz, &div_cpsdvr,
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+ &div_scr, drv_data, spi))) {
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+
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+ val = read_SSPCPSR(drv_data->ioaddr);
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+ val = val & ~SSPCPSR_SCR_MASK;
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+ val = val | div_cpsdvr;
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info (&spi->dev, "SSPCPSR: 0x%X\n", val);
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+#endif
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+ write_SSPCPSR(val, drv_data->ioaddr);
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+
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+ val = read_SSPCR0(drv_data->ioaddr);
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+ val = val & ~SSPCR0_SCR_MASK;
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+ val = val | (div_scr << SSPCR0_SCR_SHIFT);
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info (&spi->dev, "SSPCR0: 0x%X (div_scr: 0x%X)\n", val, div_scr);
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+#endif
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+ write_SSPCR0(val, drv_data->ioaddr);
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+ } else
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+ return -EINVAL;
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+
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+ /* reenable */
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+ val = read_SSPCR1(drv_data->ioaddr);
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+ val = val & ~SSPC1_SSE;
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+ write_SSPCR1(val, drv_data->ioaddr);
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+ val = read_SSPCR1(drv_data->ioaddr);
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+ val = val | SSPC1_SSE;
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+ write_SSPCR1(val, drv_data->ioaddr);
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+#ifdef SPI_EP93XX_DEBUG
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+ dev_info (&spi->dev, "Loopback mode: %s\n", (val & SSPC1_LBM) ? "On" : "Off");
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+#endif
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+
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+ return 0;
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+}
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+
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+static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
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+{
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+ struct driver_data *drv_data;
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+ unsigned long flags;
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+ int status = 0;
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+
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+ m->actual_length = 0;
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+ m->status = -EINPROGRESS;
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+
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+ drv_data = spi_master_get_devdata(spi->master);
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+
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+ spin_lock_irqsave(&drv_data->lock, flags);
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+ if (!spi->max_speed_hz)
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+ status = -ENETDOWN;
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+ else {
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+ list_add_tail(&m->queue, &drv_data->queue);
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+ queue_work(drv_data->workqueue, &drv_data->work);
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+ }
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+ spin_unlock_irqrestore(&drv_data->lock, flags);
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+ return status;
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+}
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+
|
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+static void ep93xx_work(struct work_struct *work)
|
|
+{
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+ struct driver_data *drv_data =
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+ container_of(work, struct driver_data, work);
|
|
+ unsigned long flags;
|
|
+
|
|
+ spin_lock_irqsave(&drv_data->lock, flags);
|
|
+ drv_data->busy = 1;
|
|
+
|
|
+ while (!list_empty(&drv_data->queue)) {
|
|
+ struct spi_message *m;
|
|
+ struct spi_device *spi;
|
|
+ struct spi_transfer *t = NULL;
|
|
+ int status;
|
|
+
|
|
+ m = container_of(drv_data->queue.next, struct spi_message,
|
|
+ queue);
|
|
+ list_del_init(&m->queue);
|
|
+ spin_unlock_irqrestore(&drv_data->lock, flags);
|
|
+
|
|
+ spi = m->spi;
|
|
+ status = 0;
|
|
+
|
|
+ list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
+
|
|
+ if (!t->tx_buf && !t->rx_buf && t->len) {
|
|
+ status = -EINVAL;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (t->len) {
|
|
+ if (!m->is_dma_mapped) {
|
|
+ t->rx_dma = 0;
|
|
+ t->tx_dma = 0;
|
|
+ }
|
|
+ if (t->bits_per_word <= 8)
|
|
+ status = ep93xx_txrx_8(spi, t);
|
|
+ else
|
|
+ status = ep93xx_txrx_16(spi, t);
|
|
+ }
|
|
+
|
|
+ if (status != t->len) {
|
|
+ if (status > 0)
|
|
+ status = -EMSGSIZE;
|
|
+ break;
|
|
+ }
|
|
+ m->actual_length += status;
|
|
+ status = 0;
|
|
+
|
|
+ /* protocol tweaks before next transfer */
|
|
+ if (t->delay_usecs)
|
|
+ udelay(t->delay_usecs);
|
|
+
|
|
+ if (t->transfer_list.next == &m->transfers)
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ m->status = status;
|
|
+ m->complete(m->context);
|
|
+
|
|
+ spin_lock_irqsave(&drv_data->lock, flags);
|
|
+ }
|
|
+ drv_data->busy = 0;
|
|
+ spin_unlock_irqrestore(&drv_data->lock, flags);
|
|
+}
|
|
+
|
|
+static irqreturn_t ssp_int(int irq, void *dev_id)
|
|
+{
|
|
+ struct driver_data *drv_data = dev_id;
|
|
+ u8 status;
|
|
+ status = read_SSPIIR(drv_data->ioaddr);
|
|
+
|
|
+ if (status & SSPIIR_RORIS) {
|
|
+ dev_err(&drv_data->pdev->dev, "SPI rx overrun.\n");
|
|
+
|
|
+ /* We clear the overrun here ! */
|
|
+ write_SSPICR(0, drv_data->ioaddr);
|
|
+ }
|
|
+
|
|
+ /* RX interrupt */
|
|
+ if (status & SSPIIR_RIS)
|
|
+ dev_info(&drv_data->pdev->dev, "SPI RX interrupt\n");
|
|
+
|
|
+ /* TX interrupt */
|
|
+ if (status & SSPIIR_TIS)
|
|
+ dev_info(&drv_data->pdev->dev, "SPI TX interrupt\n");
|
|
+
|
|
+ write_SSPICR(0, drv_data->ioaddr);
|
|
+ return IRQ_HANDLED;
|
|
+}
|
|
+
|
|
+static int __init ep93xx_spi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct spi_master *master;
|
|
+ struct driver_data *drv_data = 0;
|
|
+ struct resource *memory_resource;
|
|
+ int status = 0;
|
|
+ u16 val;
|
|
+
|
|
+ /* Allocate master with space for drv_data and null dma buffer */
|
|
+ master = spi_alloc_master(dev, sizeof(struct driver_data));
|
|
+ if (!master) {
|
|
+ dev_err(&pdev->dev, "cannot alloc spi_master\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+ drv_data = spi_master_get_devdata(master);
|
|
+ drv_data->master = master;
|
|
+ drv_data->pdev = pdev;
|
|
+
|
|
+ master->num_chipselect = EP93XX_GPIO_LINE_H(7) + 1;
|
|
+ master->bus_num = pdev->id;
|
|
+ master->setup = ep93xx_spi_setup;
|
|
+ master->transfer = ep93xx_spi_transfer;
|
|
+
|
|
+ spin_lock_init(&drv_data->lock);
|
|
+ INIT_LIST_HEAD(&drv_data->queue);
|
|
+
|
|
+ /* Setup register addresses */
|
|
+ memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ if (!memory_resource) {
|
|
+ dev_err(&pdev->dev, "memory resources not defined\n");
|
|
+ status = -EIO;
|
|
+ goto out_error_master_alloc;
|
|
+ } else {
|
|
+ drv_data->ioaddr = ioremap(memory_resource->start,
|
|
+ memory_resource->end - memory_resource->start);
|
|
+ if (drv_data->ioaddr == NULL) {
|
|
+ dev_err(&pdev->dev, "ioremap failed\n");
|
|
+ status = -EIO;
|
|
+ goto out_error_master_alloc;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* Attach to IRQ */
|
|
+ drv_data->irq = platform_get_irq(pdev, 0);
|
|
+ if (drv_data->irq < 0)
|
|
+ return drv_data->irq;
|
|
+
|
|
+ if (drv_data->irq <= 0) {
|
|
+ dev_err(&pdev->dev, "IRQ resource not defined\n");
|
|
+ status = -ENODEV;
|
|
+ goto out_error_master_alloc;
|
|
+ }
|
|
+
|
|
+ status = request_irq(drv_data->irq, ssp_int, 0, "ep93xx-spi", drv_data);
|
|
+ if (status < 0) {
|
|
+ dev_err(&pdev->dev, "cannot get SPI IRQ 0\n");
|
|
+ goto out_error_master_alloc;
|
|
+ }
|
|
+
|
|
+ /* SSP default configuration, enable */
|
|
+ write_SSPCR1(SSPC1_SSE, drv_data->ioaddr);
|
|
+
|
|
+ /* run as master */
|
|
+ val = read_SSPCR1(drv_data->ioaddr);
|
|
+ val = val & ~SSPC1_MS;
|
|
+ write_SSPCR1(val, drv_data->ioaddr);
|
|
+
|
|
+ /* frame format to Motorola SPI Format */
|
|
+ val = read_SSPCR0(drv_data->ioaddr);
|
|
+ val = val & ~SSPCR0_FRF_MASK ;
|
|
+ val = val | SSPCR0_FRF_MOTOROLA;
|
|
+ write_SSPCR0(val, drv_data->ioaddr);
|
|
+
|
|
+ /* enable interrupts */
|
|
+ val = read_SSPCR1(drv_data->ioaddr);
|
|
+ /* for now only overrun is handled */
|
|
+ /* val = val | SSPC1_RIE | SSPC1_TIE | SSPC1_RORIE; */
|
|
+ val = val | SSPC1_RORIE;
|
|
+ write_SSPCR1(val, drv_data->ioaddr);
|
|
+
|
|
+ /* SSP default configuration, re enable */
|
|
+ val = read_SSPCR1(drv_data->ioaddr);
|
|
+ val = val & ~SSPC1_SSE;
|
|
+ write_SSPCR1(val, drv_data->ioaddr);
|
|
+ val = read_SSPCR1(drv_data->ioaddr);
|
|
+ val = val | SSPC1_SSE;
|
|
+ write_SSPCR1(val, drv_data->ioaddr);
|
|
+
|
|
+ /* Register with the SPI framework */
|
|
+ platform_set_drvdata(pdev, drv_data);
|
|
+ status = spi_register_master(master);
|
|
+ if (status != 0) {
|
|
+ dev_err(&pdev->dev, "cannot register SPI master\n");
|
|
+ goto out_error_master_alloc;
|
|
+ } else
|
|
+ dev_info(&pdev->dev, "SPI Controller initalized\n");
|
|
+
|
|
+ INIT_WORK(&drv_data->work, ep93xx_work);
|
|
+ spin_lock_init(&drv_data->lock);
|
|
+ INIT_LIST_HEAD(&drv_data->queue);
|
|
+
|
|
+ /* this task is the only thing to touch the SPI bits */
|
|
+ drv_data->busy = 0;
|
|
+ drv_data->workqueue = create_singlethread_workqueue(
|
|
+ dev_name(drv_data->master->dev.parent));
|
|
+/* drv_data->master->cdev.dev->bus_id); */
|
|
+ if (drv_data->workqueue == NULL) {
|
|
+ status = -EBUSY;
|
|
+ goto out_error_free_irq;
|
|
+ }
|
|
+
|
|
+ return status;
|
|
+
|
|
+out_error_free_irq:
|
|
+ free_irq(drv_data->irq, master);
|
|
+out_error_master_alloc:
|
|
+ if (drv_data->ioaddr != NULL)
|
|
+ iounmap(drv_data->ioaddr);
|
|
+ spi_master_put(master);
|
|
+ return status;
|
|
+}
|
|
+
|
|
+static int __exit ep93xx_spi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct driver_data *drv_data = platform_get_drvdata(pdev);
|
|
+ u8 val;
|
|
+
|
|
+ WARN_ON(!list_empty(&drv_data->queue));
|
|
+
|
|
+ destroy_workqueue(drv_data->workqueue);
|
|
+
|
|
+ /* switch off SSP*/
|
|
+ val = read_SSPCR1(drv_data->ioaddr);
|
|
+ val = val & ~SSPC1_SSE;
|
|
+ write_SSPCR1(val, drv_data->ioaddr);
|
|
+
|
|
+ /* release irqs */
|
|
+ if (drv_data->irq > 0)
|
|
+ free_irq(drv_data->irq, drv_data);
|
|
+
|
|
+ /* Disconnect from the SPI framework */
|
|
+ spi_unregister_master(drv_data->master);
|
|
+ spi_master_put(drv_data->master);
|
|
+
|
|
+ if (drv_data->ioaddr != NULL)
|
|
+ iounmap(drv_data->ioaddr);
|
|
+
|
|
+ /* Prevent double remove */
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+static int ep93xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int ep93xx_spi_resume(struct platform_device *pdev)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#else
|
|
+#define ep93xx_spi_suspend NULL
|
|
+#define ep93xx_spi_resume NULL
|
|
+#endif
|
|
+
|
|
+struct platform_driver ep93xx_spi_device = {
|
|
+ .remove = __exit_p(ep93xx_spi_remove),
|
|
+#ifdef CONFIG_PM
|
|
+ .suspend = ep93xx_spi_suspend,
|
|
+ .resume = ep93xx_spi_resume,
|
|
+#endif
|
|
+ .driver = {
|
|
+ .name = "ep93xx-spi",
|
|
+ .bus = &spi_bus_type,
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+int __init ep93xx_spi_init(void)
|
|
+{
|
|
+ return platform_driver_probe(&ep93xx_spi_device, ep93xx_spi_probe);
|
|
+}
|
|
+
|
|
+void __exit ep93xx_spi_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&ep93xx_spi_device);
|
|
+}
|
|
+
|
|
+module_init(ep93xx_spi_init);
|
|
+module_exit(ep93xx_spi_exit);
|
|
+
|
|
+MODULE_DESCRIPTION("EP93XX SPI Driver");
|
|
+MODULE_AUTHOR("Manfred Gruber, <m.gruber@tirol.com>");
|
|
+MODULE_LICENSE("GPL");
|