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261 lines
6.1 KiB
C
261 lines
6.1 KiB
C
/*
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* JzRISC lcd controller
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*
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* xiangfu liu <xiangfu.z@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __JZLCD_H__
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#define __JZLCD_H__
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#include <asm/io.h>
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/*
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* change u-boot macro to celinux macro
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*/
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/* Chip type */
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#if defined(CONFIG_JZ4740)
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#define CONFIG_MIPS_JZ4740 1
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#endif
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/* board type */
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#if defined(CONFIG_NANONOTE)
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#define CONFIG_MIPS_JZ4740_PI 1
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#endif
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#define mdelay(n) udelay((n)*1000)
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/*
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* change u-boot macro to celinux macro
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*/
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#define NR_PALETTE 256
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struct lcd_desc{
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unsigned int next_desc; /* LCDDAx */
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unsigned int databuf; /* LCDSAx */
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unsigned int frame_id; /* LCDFIDx */
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unsigned int cmd; /* LCDCMDx */
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};
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#define MODE_MASK 0x0f
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#define MODE_TFT_GEN 0x00
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#define MODE_TFT_SHARP 0x01
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#define MODE_TFT_CASIO 0x02
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#define MODE_TFT_SAMSUNG 0x03
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#define MODE_CCIR656_NONINT 0x04
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#define MODE_CCIR656_INT 0x05
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#define MODE_STN_COLOR_SINGLE 0x08
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#define MODE_STN_MONO_SINGLE 0x09
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#define MODE_STN_COLOR_DUAL 0x0a
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#define MODE_STN_MONO_DUAL 0x0b
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#define MODE_8BIT_SERIAL_TFT 0x0c
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#define MODE_TFT_18BIT (1<<7)
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#define STN_DAT_PIN1 (0x00 << 4)
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#define STN_DAT_PIN2 (0x01 << 4)
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#define STN_DAT_PIN4 (0x02 << 4)
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#define STN_DAT_PIN8 (0x03 << 4)
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#define STN_DAT_PINMASK STN_DAT_PIN8
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#define STFT_PSHI (1 << 15)
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#define STFT_CLSHI (1 << 14)
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#define STFT_SPLHI (1 << 13)
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#define STFT_REVHI (1 << 12)
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#define SYNC_MASTER (0 << 16)
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#define SYNC_SLAVE (1 << 16)
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#define DE_P (0 << 9)
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#define DE_N (1 << 9)
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#define PCLK_P (0 << 10)
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#define PCLK_N (1 << 10)
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#define HSYNC_P (0 << 11)
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#define HSYNC_N (1 << 11)
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#define VSYNC_P (0 << 8)
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#define VSYNC_N (1 << 8)
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#define DATA_NORMAL (0 << 17)
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#define DATA_INVERSE (1 << 17)
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/* Jz LCDFB supported I/O controls. */
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#define FBIOSETBACKLIGHT 0x4688
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#define FBIODISPON 0x4689
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#define FBIODISPOFF 0x468a
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#define FBIORESET 0x468b
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#define FBIOPRINT_REG 0x468c
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/*
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* LCD panel specific definition
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*/
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#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
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#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
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#define MODE 0xcd /* 24bit parellel RGB */
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#endif
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#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
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#define MODE 0xc9 /* 8bit serial RGB */
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#endif
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#if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */
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#define SPEN (32*2+21) /*LCD_SPL */
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#define SPCK (32*2+23) /*LCD_CLS */
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#define SPDA (32*2+22) /*LCD_D12 */
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#define LCD_RET (32*3+27)
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#else
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#error "cpu/misp/Jzlcd.h, please define SPI pins on your board."
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#endif
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#define __spi_write_reg1(reg, val) \
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do { \
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unsigned char no;\
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unsigned short value;\
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unsigned char a=0;\
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unsigned char b=0;\
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a=reg;\
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b=val;\
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__gpio_set_pin(SPEN);\
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__gpio_set_pin(SPCK);\
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__gpio_clear_pin(SPDA);\
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__gpio_clear_pin(SPEN);\
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udelay(25);\
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value=((a<<8)|(b&0xFF));\
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for(no=0;no<16;no++)\
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{\
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__gpio_clear_pin(SPCK);\
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if((value&0x8000)==0x8000)\
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__gpio_set_pin(SPDA);\
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else\
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__gpio_clear_pin(SPDA);\
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udelay(25);\
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__gpio_set_pin(SPCK);\
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value=(value<<1); \
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udelay(25);\
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}\
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__gpio_set_pin(SPEN);\
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udelay(100);\
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} while (0)
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#define __spi_write_reg(reg, val) \
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do {\
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__spi_write_reg1((reg<<2|2), val);\
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udelay(100); \
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}while(0)
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#define __lcd_special_pin_init() \
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do { \
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__gpio_as_output(SPEN); /* use SPDA */\
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__gpio_as_output(SPCK); /* use SPCK */\
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__gpio_as_output(SPDA); /* use SPDA */\
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__gpio_as_output(LCD_RET);\
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} while (0)
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#if defined(CONFIG_NANONOTE)
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#define __lcd_special_on() \
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do { \
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udelay(50);\
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__spi_write_reg1(0x05, 0x16); \
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__spi_write_reg1(0x04, 0x0b); \
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__spi_write_reg1(0x07, 0x8d); \
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__spi_write_reg1(0x01, 0x95); \
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__spi_write_reg1(0x08, 0xc0); \
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__spi_write_reg1(0x03, 0x40); \
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__spi_write_reg1(0x06, 0x15); \
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__spi_write_reg1(0x05, 0xd7); \
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} while (0) /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */
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#define __lcd_special_off() \
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do { \
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__spi_write_reg1(0x05, 0x5e); \
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} while (0)
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#endif /* CONFIG_NANONOTE */
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#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
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#ifndef __lcd_special_pin_init
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#define __lcd_special_pin_init()
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#endif
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#ifndef __lcd_special_on
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#define __lcd_special_on()
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#endif
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#ifndef __lcd_special_off
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#define __lcd_special_off()
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#endif
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/*
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* Platform specific definition
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*/
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#if defined(CONFIG_MIPS_JZ4740_PI)
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/* 100 level: 0,1,...,100 */
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#define __lcd_set_backlight_level(n)\
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do { \
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__gpio_as_output(32*3+27); \
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__gpio_set_pin(32*3+27); \
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} while (0)
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#define __lcd_close_backlight() \
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do { \
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__gpio_as_output(GPIO_PWM); \
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__gpio_clear_pin(GPIO_PWM); \
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} while (0)
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#define __lcd_display_pin_init() \
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do { \
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__gpio_as_output(GPIO_DISP_OFF_N); \
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__cpm_start_tcu(); \
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__lcd_special_pin_init(); \
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} while (0)
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/* __lcd_set_backlight_level(100); \*/
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#define __lcd_display_on() \
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do { \
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__gpio_set_pin(GPIO_DISP_OFF_N); \
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__lcd_special_on(); \
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} while (0)
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#define __lcd_display_off() \
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do { \
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__lcd_special_off(); \
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__gpio_clear_pin(GPIO_DISP_OFF_N); \
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} while (0)
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#endif /* CONFIG_MIPS_JZ4740_PI) */
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/*****************************************************************************
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* LCD display pin dummy macros
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*****************************************************************************/
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#ifndef __lcd_display_pin_init
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#define __lcd_display_pin_init()
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#endif
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#ifndef __lcd_display_on
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#define __lcd_display_on()
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#endif
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#ifndef __lcd_display_off
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#define __lcd_display_off()
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#endif
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#ifndef __lcd_set_backlight_level
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#define __lcd_set_backlight_level(n)
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#endif
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