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189 lines
5.3 KiB
Diff
189 lines
5.3 KiB
Diff
From patchwork Mon Jan 29 05:11:16 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [02/15] ARM: dts: ipq4019: Add a few peripheral nodes
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From: Sricharan R <sricharan@codeaurora.org>
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X-Patchwork-Id: 10189263
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Message-Id: <1517202689-14212-3-git-send-email-sricharan@codeaurora.org>
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To: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com,
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linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org,
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catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org,
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bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
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linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org
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Cc: sricharan@codeaurora.org
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Date: Mon, 29 Jan 2018 10:41:16 +0530
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Now with the driver updates for some peripherals being there,
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add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
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peripheral support.
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
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1 file changed, 134 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -25,7 +25,9 @@
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aliases {
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spi0 = &spi_0;
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+ spi1 = &spi_1;
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i2c0 = &i2c_0;
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+ i2c1 = &i2c_1;
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};
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cpus {
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@@ -190,6 +192,22 @@
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */
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+ compatible = "qcom,spi-qup-v2.2.1";
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+ reg = <0x78b6000 0x600>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
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+ dma-names = "rx", "tx";
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status = "disabled";
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};
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@@ -202,9 +220,24 @@
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clock-names = "iface", "core";
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#address-cells = <1>;
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#size-cells = <0>;
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+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
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+ dma-names = "rx", "tx";
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status = "disabled";
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};
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+ i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
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+ compatible = "qcom,i2c-qup-v2.2.1";
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+ reg = <0x78b8000 0x600>;
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+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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+ clock-names = "iface", "core";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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cryptobam: dma@8e04000 {
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compatible = "qcom,bam-v1.7.0";
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@@ -311,6 +344,101 @@
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reg = <0x4ab000 0x4>;
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};
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+ pcie0: pci@40000000 {
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+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
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+ reg = <0x40000000 0xf1d
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+ 0x40000f20 0xa8
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+ 0x80000 0x2000
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+ 0x40100000 0x1000>;
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+ reg-names = "dbi", "elbi", "parf", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
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+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
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+
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
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+ <&gcc GCC_PCIE_AXI_M_CLK>,
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+ <&gcc GCC_PCIE_AXI_S_CLK>;
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+ clock-names = "aux",
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+ "master_bus",
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+ "slave_bus";
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+
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+ resets = <&gcc PCIE_AXI_M_ARES>,
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+ <&gcc PCIE_AXI_S_ARES>,
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+ <&gcc PCIE_PIPE_ARES>,
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+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
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+ <&gcc PCIE_AXI_S_XPU_ARES>,
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+ <&gcc PCIE_PARF_XPU_ARES>,
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+ <&gcc PCIE_PHY_ARES>,
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+ <&gcc PCIE_AXI_M_STICKY_ARES>,
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+ <&gcc PCIE_PIPE_STICKY_ARES>,
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+ <&gcc PCIE_PWR_ARES>,
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+ <&gcc PCIE_AHB_ARES>,
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+ <&gcc PCIE_PHY_AHB_ARES>;
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+ reset-names = "axi_m",
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+ "axi_s",
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+ "pipe",
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+ "axi_m_vmid",
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+ "axi_s_xpu",
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+ "parf",
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+ "phy",
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+ "axi_m_sticky",
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+ "pipe_sticky",
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+ "pwr",
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+ "ahb",
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+ "phy_ahb";
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+
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+ status = "disabled";
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+ };
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+
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+ qpic_bam: dma@7984000 {
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+ compatible = "qcom,bam-v1.7.0";
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+ reg = <0x7984000 0x1a000>;
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+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_QPIC_CLK>;
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+ clock-names = "bam_clk";
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+ #dma-cells = <1>;
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+ qcom,ee = <0>;
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+ status = "disabled";
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+ };
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+
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+ nand: qpic-nand@79b0000 {
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+ compatible = "qcom,ipq4019-nand";
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+ reg = <0x79b0000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>;
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+ clock-names = "core", "aon";
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+
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+ dmas = <&qpic_bam 0>,
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+ <&qpic_bam 1>,
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+ <&qpic_bam 2>;
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+ dma-names = "tx", "rx", "cmd";
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+ status = "disabled";
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+
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+ nand@0 {
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+ reg = <0>;
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+
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ nand-bus-width = <8>;
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+ };
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+ };
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+
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wifi0: wifi@a000000 {
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compatible = "qcom,ipq4019-wifi";
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reg = <0xa000000 0x200000>;
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