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108 lines
3.1 KiB
Diff
108 lines
3.1 KiB
Diff
From 42cfda7eaf263248257cef40b88e06b7a0666eb4 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 17 Mar 2012 09:58:07 +0100
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Subject: [PATCH 62/73] MIPS: lantiq: fixes ar9/vr9 clock
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---
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arch/mips/lantiq/clk.h | 4 +++-
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arch/mips/lantiq/xway/clk.c | 29 ++++++++++++++++++++++++-----
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arch/mips/lantiq/xway/sysctrl.c | 13 ++++++++-----
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3 files changed, 35 insertions(+), 11 deletions(-)
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--- a/arch/mips/lantiq/clk.h
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+++ b/arch/mips/lantiq/clk.h
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@@ -56,8 +56,10 @@ extern unsigned long ltq_danube_cpu_hz(v
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extern unsigned long ltq_danube_fpi_hz(void);
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extern unsigned long ltq_danube_io_region_clock(void);
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+extern unsigned long ltq_ar9_cpu_hz(void);
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+extern unsigned long ltq_ar9_fpi_hz(void);
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+
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extern unsigned long ltq_vr9_cpu_hz(void);
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extern unsigned long ltq_vr9_fpi_hz(void);
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-extern unsigned long ltq_vr9_io_region_clock(void);
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#endif
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--- a/arch/mips/lantiq/xway/clk.c
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+++ b/arch/mips/lantiq/xway/clk.c
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@@ -217,6 +217,30 @@ unsigned long ltq_danube_cpu_hz(void)
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}
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}
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+unsigned long ltq_ar9_sys_hz(void)
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+{
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+ if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2)
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+ return CLOCK_393M;
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+ return CLOCK_333M;
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+}
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+
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+unsigned long ltq_ar9_fpi_hz(void)
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+{
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+ unsigned long sys = ltq_ar9_sys_hz();
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+
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+ if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0))
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+ return sys;
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+ return sys >> 1;
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+}
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+
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+unsigned long ltq_ar9_cpu_hz(void)
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+{
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+ if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2))
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+ return ltq_ar9_fpi_hz();
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+ else
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+ return ltq_ar9_sys_hz();
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+}
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+
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unsigned long ltq_danube_fpi_hz(void)
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{
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unsigned long ddr_clock = DDR_HZ;
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@@ -299,11 +323,6 @@ unsigned long ltq_vr9_fpi_hz(void)
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return clk;
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}
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-unsigned long ltq_vr9_io_region_clock(void)
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-{
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- return ltq_vr9_fpi_hz();
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-}
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-
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unsigned long ltq_vr9_fpi_bus_clock(int fpi)
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{
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return ltq_vr9_fpi_hz();
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -237,6 +237,8 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU);
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if (!ltq_is_vr9())
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clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
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+ if (!ltq_is_ase())
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+ clkdev_add_pci();
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if (ltq_is_ase()) {
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if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
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clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
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@@ -246,7 +248,7 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
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} else if (ltq_is_vr9()) {
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clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
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- ltq_vr9_io_region_clock());
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+ ltq_vr9_fpi_hz());
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clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY);
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clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK);
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clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI);
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@@ -259,11 +261,12 @@ void __init ltq_soc_init(void)
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PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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PMU_PPE_QSB);
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+ } else if (ltq_is_ar9()) {
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+ clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
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+ ltq_ar9_fpi_hz());
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+ clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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- ltq_danube_io_region_clock());
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- clkdev_add_pci();
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- if (ltq_is_ar9())
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- clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
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+ ltq_danube_io_region_clock());
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}
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}
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