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1057 lines
26 KiB
Diff
1057 lines
26 KiB
Diff
From 80ca93f1a5590529e39560099a71edb03897050e Mon Sep 17 00:00:00 2001
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From: Mingkai Hu <mingkai.hu@nxp.com>
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Date: Wed, 11 May 2016 11:29:51 +0800
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Subject: [PATCH 131/141] arm64/ls1046a: add DTS for Freescale LS1046A SoC
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LS1046a is an SoC with 4 ARMv8 A72 cores and most other IP blocks
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similar to LS1043a which complies to Chassis 2.1 spec.
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Following levels of DTSI/DTS files have been created for the
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LS1046A SoC family:
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- fsl-ls1046a.dtsi:
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DTS-Include file for FSL LS1046A SoC.
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Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
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Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1029 ++++++++++++++++++++++++
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1 file changed, 1029 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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@@ -0,0 +1,1029 @@
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+/*
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+ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
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+ *
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+ * Copyright 2016, Freescale Semiconductor
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+ *
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+ * Mingkai Hu <mingkai.hu@nxp.com>
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+ *
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+ * This file is dual-licensed: you can use it either under the terms
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+ * of the GPLv2 or the X11 license, at your option. Note that this dual
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+ * licensing only applies to this file, and not this project as a
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+ * whole.
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+ *
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+ * a) This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Or, alternatively,
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+ *
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+ * b) Permission is hereby granted, free of charge, to any person
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+ * obtaining a copy of this software and associated documentation
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+ * files (the "Software"), to deal in the Software without
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+ * restriction, including without limitation the rights to use,
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+ * copy, modify, merge, publish, distribute, sublicense, and/or
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+ * sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following
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+ * conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be
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+ * included in all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+/ {
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+ compatible = "fsl,ls1046a";
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+ interrupt-parent = <&gic>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ aliases {
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+ ethernet0 = &fm1mac1;
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+ ethernet1 = &fm1mac2;
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+ ethernet2 = &fm1mac3;
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+ ethernet3 = &fm1mac4;
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+ ethernet4 = &fm1mac5;
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+ ethernet5 = &fm1mac6;
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+ ethernet6 = &fm1mac9;
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72";
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+ reg = <0x0>;
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+ clocks = <&clockgen 1 0>;
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+ next-level-cache = <&l2>;
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+ };
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+
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72";
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+ reg = <0x1>;
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+ clocks = <&clockgen 1 0>;
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+ next-level-cache = <&l2>;
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+ };
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+
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72";
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+ reg = <0x2>;
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+ clocks = <&clockgen 1 0>;
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+ next-level-cache = <&l2>;
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+ };
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+
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a72";
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+ reg = <0x3>;
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+ clocks = <&clockgen 1 0>;
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+ next-level-cache = <&l2>;
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+ };
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+
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+ l2: l2-cache {
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+ compatible = "cache";
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+ };
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+ };
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+
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+ memory@80000000 {
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+ device_type = "memory";
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+ reg = <0x0 0x80000000 0 0x80000000>;
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+ /* DRAM space 1, size: 2GiB DRAM */
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+ };
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+
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+ sysclk: sysclk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <100000000>;
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+ clock-output-names = "sysclk";
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+ };
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+
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+ timer {
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+ compatible = "arm,armv8-timer";
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+ interrupts = <1 13 0x1>, /* Physical Secure PPI */
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+ <1 14 0x1>, /* Physical Non-Secure PPI */
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+ <1 11 0x1>, /* Virtual PPI */
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+ <1 10 0x1>; /* Hypervisor PPI */
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+ arm,reread-timer;
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+ };
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+
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+ pmu {
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+ compatible = "arm,armv8-pmuv3";
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+ interrupts = <0 106 0x4>,
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+ <0 107 0x4>,
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+ <0 95 0x4>,
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+ <0 97 0x4>;
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+ interrupt-affinity = <&cpu0>,
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+ <&cpu1>,
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+ <&cpu2>,
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+ <&cpu3>;
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+ };
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+
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+ gic: interrupt-controller@1400000 {
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+ compatible = "arm,gic-400";
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+ #interrupt-cells = <3>;
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+ interrupt-controller;
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+ reg = <0x0 0x1410000 0 0x10000>, /* GICD */
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+ <0x0 0x1420000 0 0x20000>, /* GICC */
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+ <0x0 0x1440000 0 0x20000>, /* GICH */
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+ <0x0 0x1460000 0 0x20000>; /* GICV */
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+ interrupts = <1 9 0xf08>;
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+ };
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+
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+ soc {
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+ compatible = "simple-bus";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ clockgen: clocking@1ee1000 {
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+ compatible = "fsl,ls1046a-clockgen";
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+ reg = <0x0 0x1ee1000 0x0 0x1000>;
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+ #clock-cells = <2>;
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+ clocks = <&sysclk>;
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+ };
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+
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+ scfg: scfg@1570000 {
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+ compatible = "fsl,ls1046a-scfg", "syscon";
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+ reg = <0x0 0x1570000 0x0 0x10000>;
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+ big-endian;
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+ };
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+
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+ reset: reset@1ee00b0 {
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+ compatible = "fsl,ls-reset";
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+ reg = <0x0 0x1ee00b0 0x0 0x4>;
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+ big-endian;
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+ };
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+
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+ rcpm: rcpm@1ee2000 {
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+ compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1";
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+ reg = <0x0 0x1ee2000 0x0 0x10000>;
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+ };
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+
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+ ifc: ifc@1530000 {
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+ compatible = "fsl,ifc", "simple-bus";
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+ reg = <0x0 0x1530000 0x0 0x10000>;
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+ interrupts = <0 43 0x4>;
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+ };
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+
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+ esdhc: esdhc@1560000 {
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+ compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
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+ reg = <0x0 0x1560000 0x0 0x10000>;
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+ interrupts = <0 62 0x4>;
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+ clock-frequency = <0>;
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+ voltage-ranges = <1800 1800 3300 3300>;
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+ sdhci,auto-cmd12;
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+ big-endian;
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+ bus-width = <4>;
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+ };
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+
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+ qman: qman@1880000 {
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+ compatible = "fsl,qman";
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+ reg = <0x00 0x1880000 0x0 0x10000>;
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+ interrupts = <0 45 0x4>;
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+ };
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+
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+ bman: bman@1890000 {
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+ compatible = "fsl,bman";
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+ reg = <0x00 0x1890000 0x0 0x10000>;
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+ interrupts = <0 45 0x4>;
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+ };
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+
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+ fman0: fman@1a00000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ cell-index = <0>;
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+ compatible = "fsl,fman", "simple-bus";
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+ ranges = <0x0 0x00 0x1a00000 0x100000>;
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+ reg = <0x00 0x1a00000 0x0 0x100000>;
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+ interrupts = <0 44 0x4>, <0 45 0x4>;
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+ clocks = <&clockgen 3 0>;
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+ clock-names = "fmanclk";
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+
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+ cc {
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+ compatible = "fsl,fman-cc";
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+ };
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+
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+ muram@0 {
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+ compatible = "fsl,fman-muram";
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+ reg = <0x0 0x60000>;
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+ };
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+
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+ bmi@80000 {
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+ compatible = "fsl,fman-bmi";
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+ reg = <0x80000 0x400>;
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+ };
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+
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+ qmi@80400 {
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+ compatible = "fsl,fman-qmi";
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+ reg = <0x80400 0x400>;
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+ };
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+
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+ fman0_oh1: port@82000 {
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+ cell-index = <0>;
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+ compatible = "fsl,fman-port-oh";
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+ reg = <0x82000 0x1000>;
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+ };
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+
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+ fman0_oh2: port@83000 {
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+ cell-index = <1>;
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+ compatible = "fsl,fman-port-oh";
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+ reg = <0x83000 0x1000>;
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+ };
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+
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+ fman0_oh3: port@84000 {
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+ cell-index = <2>;
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+ compatible = "fsl,fman-port-oh";
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+ reg = <0x84000 0x1000>;
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+ };
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+
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+ fman0_oh4: port@85000 {
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+ cell-index = <3>;
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+ compatible = "fsl,fman-port-oh";
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+ reg = <0x85000 0x1000>;
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+ };
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+
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+ fman0_oh5: port@86000 {
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+ cell-index = <4>;
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+ compatible = "fsl,fman-port-oh";
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+ reg = <0x86000 0x1000>;
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+ };
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+
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+ fman0_oh6: port@87000 {
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+ cell-index = <5>;
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+ compatible = "fsl,fman-port-oh";
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+ reg = <0x87000 0x1000>;
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+ };
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+
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+ policer@c0000 {
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+ compatible = "fsl,fman-policer";
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+ reg = <0xc0000 0x1000>;
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+ };
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+
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+ keygen@c1000 {
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+ compatible = "fsl,fman-keygen";
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+ reg = <0xc1000 0x1000>;
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+ };
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+
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+ dma@c2000 {
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+ compatible = "fsl,fman-dma";
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+ reg = <0xc2000 0x1000>;
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+ };
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+
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+ fpm@c3000 {
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+ compatible = "fsl,fman-fpm";
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+ reg = <0xc3000 0x1000>;
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+ };
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+
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+ parser@c7000 {
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+ compatible = "fsl,fman-parser";
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+ reg = <0xc7000 0x1000>;
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+ };
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+
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+ vsps@dc000 {
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+ compatible = "fsl,fman-vsps";
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+ reg = <0xdc000 0x1000>;
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+ };
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+
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+ mdio0: mdio@fc000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,fman-memac-mdio";
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+ reg = <0xfc000 0x1000>;
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+ };
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+
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+ xmdio0: mdio@fd000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,fman-memac-mdio";
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+ reg = <0xfd000 0x1000>;
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+ };
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+
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+ fman0_rx0: port@88000 {
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+ cell-index = <0>;
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+ compatible = "fsl,fman-port-1g-rx";
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+ reg = <0x88000 0x1000>;
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+ };
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+
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+ fman0_tx0: port@a8000 {
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+ cell-index = <0>;
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+ compatible = "fsl,fman-port-1g-tx";
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+ reg = <0xa8000 0x1000>;
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+ };
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+
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+ fm1mac1: ethernet@e0000 {
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+ cell-index = <0>;
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+ compatible = "fsl,fman-memac";
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+ reg = <0xe0000 0x1000>;
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+ fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
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+ ptimer-handle = <&ptp_timer0>;
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+ };
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+
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+ mdio@e1000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,fman-memac-mdio";
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+ reg = <0xe1000 0x1000>;
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+ };
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+
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+ fman0_rx1: port@89000 {
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+ cell-index = <1>;
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+ compatible = "fsl,fman-port-1g-rx";
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+ reg = <0x89000 0x1000>;
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+ };
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+
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+ fman0_tx1: port@a9000 {
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+ cell-index = <1>;
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+ compatible = "fsl,fman-port-1g-tx";
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+ reg = <0xa9000 0x1000>;
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+ };
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+
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+ fm1mac2: ethernet@e2000 {
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+ cell-index = <1>;
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+ compatible = "fsl,fman-memac";
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+ reg = <0xe2000 0x1000>;
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+ fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
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+ ptimer-handle = <&ptp_timer0>;
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+ };
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+
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+ mdio@e3000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "fsl,fman-memac-mdio";
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+ reg = <0xe3000 0x1000>;
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+ };
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+
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+ fman0_rx2: port@8a000 {
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+ cell-index = <2>;
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+ compatible = "fsl,fman-port-1g-rx";
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+ reg = <0x8a000 0x1000>;
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+ };
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+
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+ fman0_tx2: port@aa000 {
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+ cell-index = <2>;
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+ compatible = "fsl,fman-port-1g-tx";
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+ reg = <0xaa000 0x1000>;
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+ };
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+
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+ fm1mac3: ethernet@e4000 {
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+ cell-index = <2>;
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+ compatible = "fsl,fman-memac";
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+ reg = <0xe4000 0x1000>;
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+ fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
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+ ptimer-handle = <&ptp_timer0>;
|
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+ };
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+
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+ mdio@e5000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
|
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+ compatible = "fsl,fman-memac-mdio";
|
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+ reg = <0xe5000 0x1000>;
|
|
+ };
|
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+
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+ fman0_rx3: port@8b000 {
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+ cell-index = <3>;
|
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+ compatible = "fsl,fman-port-1g-rx";
|
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+ reg = <0x8b000 0x1000>;
|
|
+ };
|
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+
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+ fman0_tx3: port@ab000 {
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+ cell-index = <3>;
|
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+ compatible = "fsl,fman-port-1g-tx";
|
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+ reg = <0xab000 0x1000>;
|
|
+ };
|
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+
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+ fm1mac4: ethernet@e6000 {
|
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+ cell-index = <3>;
|
|
+ compatible = "fsl,fman-memac";
|
|
+ reg = <0xe6000 0x1000>;
|
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+ fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
|
|
+ ptimer-handle = <&ptp_timer0>;
|
|
+ };
|
|
+
|
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+ mdio@e7000 {
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+ #address-cells = <1>;
|
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+ #size-cells = <0>;
|
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+ compatible = "fsl,fman-memac-mdio";
|
|
+ reg = <0xe7000 0x1000>;
|
|
+ };
|
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+
|
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+ fman0_rx4: port@8c000 {
|
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+ cell-index = <4>;
|
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+ compatible = "fsl,fman-port-1g-rx";
|
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+ reg = <0x8c000 0x1000>;
|
|
+ };
|
|
+
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|
+ fman0_tx4: port@ac000 {
|
|
+ cell-index = <4>;
|
|
+ compatible = "fsl,fman-port-1g-tx";
|
|
+ reg = <0xac000 0x1000>;
|
|
+ };
|
|
+
|
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+ fm1mac5: ethernet@e8000 {
|
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+ cell-index = <4>;
|
|
+ compatible = "fsl,fman-memac";
|
|
+ reg = <0xe8000 0x1000>;
|
|
+ fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
|
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+ ptimer-handle = <&ptp_timer0>;
|
|
+ };
|
|
+
|
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+ mdio@e9000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "fsl,fman-memac-mdio";
|
|
+ reg = <0xe9000 0x1000>;
|
|
+ };
|
|
+
|
|
+ fman0_rx5: port@8d000 {
|
|
+ cell-index = <5>;
|
|
+ compatible = "fsl,fman-port-1g-rx";
|
|
+ reg = <0x8d000 0x1000>;
|
|
+ };
|
|
+
|
|
+ fman0_tx5: port@ad000 {
|
|
+ cell-index = <5>;
|
|
+ compatible = "fsl,fman-port-1g-tx";
|
|
+ reg = <0xad000 0x1000>;
|
|
+ };
|
|
+
|
|
+ fm1mac6: ethernet@ea000 {
|
|
+ cell-index = <5>;
|
|
+ compatible = "fsl,fman-memac";
|
|
+ reg = <0xea000 0x1000>;
|
|
+ fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
|
|
+ ptimer-handle = <&ptp_timer0>;
|
|
+ };
|
|
+
|
|
+ mdio@eb000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "fsl,fman-memac-mdio";
|
|
+ reg = <0xeb000 0x1000>;
|
|
+ };
|
|
+
|
|
+ fman0_10g_rx0: port@90000 {
|
|
+ cell-index = <0>;
|
|
+ compatible = "fsl,fman-port-10g-rx";
|
|
+ reg = <0x90000 0x1000>;
|
|
+ };
|
|
+
|
|
+ fman0_10g_tx0: port@b0000 {
|
|
+ cell-index = <0>;
|
|
+ compatible = "fsl,fman-port-10g-tx";
|
|
+ reg = <0xb0000 0x1000>;
|
|
+ fsl,qman-channel-id = <0x800>;
|
|
+ };
|
|
+
|
|
+ fm1mac9: ethernet@f0000 {
|
|
+ cell-index = <0>;
|
|
+ compatible = "fsl,fman-memac";
|
|
+ reg = <0xf0000 0x1000>;
|
|
+ fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
|
|
+ };
|
|
+
|
|
+ mdio@f1000 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "fsl,fman-memac-mdio";
|
|
+ reg = <0xf1000 0x1000>;
|
|
+ };
|
|
+
|
|
+ ptp_timer0: rtc@fe000 {
|
|
+ compatible = "fsl,fman-rtc";
|
|
+ reg = <0xfe000 0x1000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dspi: dspi@2100000 {
|
|
+ compatible = "fsl,ls1046a-dspi", "fsl,ls1021a-v1.0-dspi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2100000 0x0 0x10000>;
|
|
+ interrupts = <0 64 0x4>;
|
|
+ clock-names = "dspi";
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ spi-num-chipselects = <5>;
|
|
+ big-endian;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ qspi: quadspi@1550000 {
|
|
+ compatible = "fsl,ls1046a-qspi", "fsl,ls1021a-qspi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x1550000 0x0 0x10000>,
|
|
+ <0x0 0x40000000 0x0 0x10000000>;
|
|
+ reg-names = "QuadSPI", "QuadSPI-memory";
|
|
+ interrupts = <0 99 0x4>;
|
|
+ clock-names = "qspi_en", "qspi";
|
|
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
|
+ big-endian;
|
|
+ fsl,qspi-has-second-chip;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@2180000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2180000 0x0 0x10000>;
|
|
+ interrupts = <0 56 0x4>;
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ dmas = <&edma0 1 39>,
|
|
+ <&edma0 1 38>;
|
|
+ dma-names = "tx", "rx";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@2190000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2190000 0x0 0x10000>;
|
|
+ interrupts = <0 57 0x4>;
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@21a0000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x21a0000 0x0 0x10000>;
|
|
+ interrupts = <0 58 0x4>;
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@21b0000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x21b0000 0x0 0x10000>;
|
|
+ interrupts = <0 59 0x4>;
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ duart0: serial@21c0500 {
|
|
+ compatible = "fsl,ns16550", "ns16550a";
|
|
+ reg = <0x00 0x21c0500 0x0 0x100>;
|
|
+ interrupts = <0 54 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ };
|
|
+
|
|
+ duart1: serial@21c0600 {
|
|
+ compatible = "fsl,ns16550", "ns16550a";
|
|
+ reg = <0x00 0x21c0600 0x0 0x100>;
|
|
+ interrupts = <0 54 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ };
|
|
+
|
|
+ duart2: serial@21d0500 {
|
|
+ compatible = "fsl,ns16550", "ns16550a";
|
|
+ reg = <0x0 0x21d0500 0x0 0x100>;
|
|
+ interrupts = <0 55 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ };
|
|
+
|
|
+ duart3: serial@21d0600 {
|
|
+ compatible = "fsl,ns16550", "ns16550a";
|
|
+ reg = <0x0 0x21d0600 0x0 0x100>;
|
|
+ interrupts = <0 55 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ };
|
|
+
|
|
+ gpio0: gpio@2300000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2300000 0x0 0x10000>;
|
|
+ interrupts = <0 66 0x4>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio1: gpio@2310000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2310000 0x0 0x10000>;
|
|
+ interrupts = <0 67 0x4>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio2: gpio@2320000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2320000 0x0 0x10000>;
|
|
+ interrupts = <0 68 0x4>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio3: gpio@2330000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2330000 0x0 0x10000>;
|
|
+ interrupts = <0 134 0x4>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ lpuart0: serial@2950000 {
|
|
+ compatible = "fsl,ls1021a-lpuart";
|
|
+ reg = <0x0 0x2950000 0x0 0x1000>;
|
|
+ interrupts = <0 48 0x4>;
|
|
+ clocks = <&clockgen 0 0>;
|
|
+ clock-names = "ipg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ lpuart1: serial@2960000 {
|
|
+ compatible = "fsl,ls1021a-lpuart";
|
|
+ reg = <0x0 0x2960000 0x0 0x1000>;
|
|
+ interrupts = <0 49 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ clock-names = "ipg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ lpuart2: serial@2970000 {
|
|
+ compatible = "fsl,ls1021a-lpuart";
|
|
+ reg = <0x0 0x2970000 0x0 0x1000>;
|
|
+ interrupts = <0 50 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ clock-names = "ipg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ lpuart3: serial@2980000 {
|
|
+ compatible = "fsl,ls1021a-lpuart";
|
|
+ reg = <0x0 0x2980000 0x0 0x1000>;
|
|
+ interrupts = <0 51 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ clock-names = "ipg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ lpuart4: serial@2990000 {
|
|
+ compatible = "fsl,ls1021a-lpuart";
|
|
+ reg = <0x0 0x2990000 0x0 0x1000>;
|
|
+ interrupts = <0 52 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ clock-names = "ipg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ lpuart5: serial@29a0000 {
|
|
+ compatible = "fsl,ls1021a-lpuart";
|
|
+ reg = <0x0 0x29a0000 0x0 0x1000>;
|
|
+ interrupts = <0 53 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ clock-names = "ipg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ftm0: ftm0@29d0000 {
|
|
+ compatible = "fsl,ftm-alarm";
|
|
+ reg = <0x0 0x29d0000 0x0 0x10000>;
|
|
+ interrupts = <0 86 0x4>;
|
|
+ big-endian;
|
|
+ rcpm-wakeup = <&rcpm 0x0 0x20000000>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ wdog0: wdog@2ad0000 {
|
|
+ compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt";
|
|
+ reg = <0x0 0x2ad0000 0x0 0x10000>;
|
|
+ interrupts = <0 83 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ clock-names = "wdog";
|
|
+ big-endian;
|
|
+ };
|
|
+
|
|
+ edma0: edma@2c00000 {
|
|
+ #dma-cells = <2>;
|
|
+ compatible = "fsl,vf610-edma";
|
|
+ reg = <0x0 0x2c00000 0x0 0x10000>,
|
|
+ <0x0 0x2c10000 0x0 0x10000>,
|
|
+ <0x0 0x2c20000 0x0 0x10000>;
|
|
+ interrupts = <0 103 0x4>,
|
|
+ <0 103 0x4>;
|
|
+ interrupt-names = "edma-tx", "edma-err";
|
|
+ dma-channels = <32>;
|
|
+ big-endian;
|
|
+ clock-names = "dmamux0", "dmamux1";
|
|
+ clocks = <&clockgen 4 1>,
|
|
+ <&clockgen 4 1>;
|
|
+ };
|
|
+
|
|
+ usb0: usb3@2f00000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0x2f00000 0x0 0x10000>;
|
|
+ interrupts = <0 60 0x4>;
|
|
+ dr_mode = "host";
|
|
+ configure-gfladj;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ };
|
|
+
|
|
+ usb1: usb3@3000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0x3000000 0x0 0x10000>;
|
|
+ interrupts = <0 61 0x4>;
|
|
+ dr_mode = "host";
|
|
+ configure-gfladj;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ };
|
|
+
|
|
+ usb2: usb3@3100000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0x3100000 0x0 0x10000>;
|
|
+ interrupts = <0 63 0x4>;
|
|
+ dr_mode = "host";
|
|
+ configure-gfladj;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ };
|
|
+
|
|
+ sata: sata@3200000 {
|
|
+ compatible = "fsl,ls1046a-ahci";
|
|
+ reg = <0x0 0x3200000 0x0 0x10000>;
|
|
+ interrupts = <0 69 0x4>;
|
|
+ clocks = <&clockgen 4 1>;
|
|
+ };
|
|
+
|
|
+ qdma: qdma@8380000 {
|
|
+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
|
|
+ reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
|
|
+ 0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
|
+ interrupts = <0 152 0x4>,
|
|
+ <0 39 0x4>;
|
|
+ interrupt-names = "qdma-error", "qdma-queue";
|
|
+ channels = <8>;
|
|
+ queues = <2>;
|
|
+ status-sizes = <64>;
|
|
+ queue-sizes = <64 64>;
|
|
+ big-endian;
|
|
+ };
|
|
+
|
|
+ msi1: msi-controller@1580000 {
|
|
+ compatible = "fsl,1s1046a-msi";
|
|
+ reg = <0x0 0x1580000 0x0 0x10000>;
|
|
+ msi-controller;
|
|
+ interrupts = <0 116 0x4>,
|
|
+ <0 111 0x4>,
|
|
+ <0 112 0x4>,
|
|
+ <0 113 0x4>;
|
|
+ };
|
|
+
|
|
+ msi2: msi-controller@1590000 {
|
|
+ compatible = "fsl,1s1046a-msi";
|
|
+ reg = <0x0 0x1590000 0x0 0x10000>;
|
|
+ msi-controller;
|
|
+ interrupts = <0 126 0x4>,
|
|
+ <0 121 0x4>,
|
|
+ <0 122 0x4>,
|
|
+ <0 123 0x4>;
|
|
+ };
|
|
+
|
|
+ msi3: msi-controller@15a0000 {
|
|
+ compatible = "fsl,1s1046a-msi";
|
|
+ reg = <0x0 0x15a0000 0x0 0x10000>;
|
|
+ msi-controller;
|
|
+ interrupts = <0 160 0x4>,
|
|
+ <0 155 0x4>,
|
|
+ <0 156 0x4>,
|
|
+ <0 157 0x4>;
|
|
+ };
|
|
+
|
|
+ pcie@3400000 {
|
|
+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
|
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 118 0x4>, /* controller interrupt */
|
|
+ <0 117 0x4>; /* PME interrupt */
|
|
+ interrupt-names = "intr", "pme";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ num-lanes = <4>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&msi1>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
|
+ <0000 0 0 2 &gic 0 110 0x4>,
|
|
+ <0000 0 0 3 &gic 0 110 0x4>,
|
|
+ <0000 0 0 4 &gic 0 110 0x4>;
|
|
+ };
|
|
+
|
|
+ pcie@3500000 {
|
|
+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
|
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 128 0x4>,
|
|
+ <0 127 0x4>;
|
|
+ interrupt-names = "intr", "pme";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ num-lanes = <2>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&msi2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
|
+ <0000 0 0 2 &gic 0 120 0x4>,
|
|
+ <0000 0 0 3 &gic 0 120 0x4>,
|
|
+ <0000 0 0 4 &gic 0 120 0x4>;
|
|
+ };
|
|
+
|
|
+ pcie@3600000 {
|
|
+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
|
+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 162 0x4>,
|
|
+ <0 161 0x4>;
|
|
+ interrupt-names = "intr", "pme";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ num-lanes = <2>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&msi3>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
|
+ <0000 0 0 2 &gic 0 154 0x4>,
|
|
+ <0000 0 0 3 &gic 0 154 0x4>,
|
|
+ <0000 0 0 4 &gic 0 154 0x4>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fsl,dpaa {
|
|
+ compatible = "fsl,ls1046a-dpaa", "simple-bus", "fsl,dpaa";
|
|
+ ethernet@0 {
|
|
+ compatible = "fsl,dpa-ethernet";
|
|
+ fsl,fman-mac = <&fm1mac1>;
|
|
+ };
|
|
+ ethernet@1 {
|
|
+ compatible = "fsl,dpa-ethernet";
|
|
+ fsl,fman-mac = <&fm1mac2>;
|
|
+ };
|
|
+ ethernet@2 {
|
|
+ compatible = "fsl,dpa-ethernet";
|
|
+ fsl,fman-mac = <&fm1mac3>;
|
|
+ };
|
|
+ ethernet@3 {
|
|
+ compatible = "fsl,dpa-ethernet";
|
|
+ fsl,fman-mac = <&fm1mac4>;
|
|
+ };
|
|
+ ethernet@4 {
|
|
+ compatible = "fsl,dpa-ethernet";
|
|
+ fsl,fman-mac = <&fm1mac5>;
|
|
+ };
|
|
+ ethernet@5 {
|
|
+ compatible = "fsl,dpa-ethernet";
|
|
+ fsl,fman-mac = <&fm1mac6>;
|
|
+ };
|
|
+ ethernet@8 {
|
|
+ compatible = "fsl,dpa-ethernet";
|
|
+ fsl,fman-mac = <&fm1mac9>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ qportals: qman-portals@500000000 {
|
|
+ ranges = <0x0 0x5 0x00000000 0x8000000>;
|
|
+ };
|
|
+ bportals: bman-portals@508000000 {
|
|
+ ranges = <0x0 0x5 0x08000000 0x8000000>;
|
|
+ };
|
|
+ reserved-memory {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+
|
|
+ bman_fbpr: bman-fbpr {
|
|
+ size = <0 0x1000000>;
|
|
+ alignment = <0 0x1000000>;
|
|
+ };
|
|
+ qman_fqd: qman-fqd {
|
|
+ size = <0 0x800000>;
|
|
+ alignment = <0 0x800000>;
|
|
+ };
|
|
+ qman_pfdr: qman-pfdr {
|
|
+ size = <0 0x2000000>;
|
|
+ alignment = <0 0x2000000>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&fman0 {
|
|
+ /* offline - 1 */
|
|
+ port@82000 {
|
|
+ fsl,qman-channel-id = <0x809>;
|
|
+ };
|
|
+
|
|
+ /* tx - 10g - 2 */
|
|
+ port@a8000 {
|
|
+ fsl,qman-channel-id = <0x802>;
|
|
+ };
|
|
+ /* tx - 10g - 3 */
|
|
+ port@a9000 {
|
|
+ fsl,qman-channel-id = <0x803>;
|
|
+ };
|
|
+ /* tx - 1g - 2 */
|
|
+ port@aa000 {
|
|
+ fsl,qman-channel-id = <0x804>;
|
|
+ };
|
|
+ /* tx - 1g - 3 */
|
|
+ port@ab000 {
|
|
+ fsl,qman-channel-id = <0x805>;
|
|
+ };
|
|
+ /* tx - 1g - 4 */
|
|
+ port@ac000 {
|
|
+ fsl,qman-channel-id = <0x806>;
|
|
+ };
|
|
+ /* tx - 1g - 5 */
|
|
+ port@ad000 {
|
|
+ fsl,qman-channel-id = <0x807>;
|
|
+ };
|
|
+ /* tx - 10g - 0 */
|
|
+ port@b0000 {
|
|
+ fsl,qman-channel-id = <0x800>;
|
|
+ };
|
|
+ /* tx - 10g - 1 */
|
|
+ port@b1000 {
|
|
+ fsl,qman-channel-id = <0x801>;
|
|
+ };
|
|
+ /* offline - 2 */
|
|
+ port@83000 {
|
|
+ fsl,qman-channel-id = <0x80a>;
|
|
+ };
|
|
+ /* offline - 3 */
|
|
+ port@84000 {
|
|
+ fsl,qman-channel-id = <0x80b>;
|
|
+ };
|
|
+ /* offline - 4 */
|
|
+ port@85000 {
|
|
+ fsl,qman-channel-id = <0x80c>;
|
|
+ };
|
|
+ /* offline - 5 */
|
|
+ port@86000 {
|
|
+ fsl,qman-channel-id = <0x80d>;
|
|
+ };
|
|
+ /* offline - 6 */
|
|
+ port@87000 {
|
|
+ fsl,qman-channel-id = <0x80e>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&bman_fbpr {
|
|
+ compatible = "fsl,bman-fbpr";
|
|
+ alloc-ranges = <0 0 0x10000 0>;
|
|
+};
|
|
+
|
|
+&qman_fqd {
|
|
+ compatible = "fsl,qman-fqd";
|
|
+ alloc-ranges = <0 0 0x10000 0>;
|
|
+};
|
|
+
|
|
+&qman_pfdr {
|
|
+ compatible = "fsl,qman-pfdr";
|
|
+ alloc-ranges = <0 0 0x10000 0>;
|
|
+};
|
|
+
|
|
+/include/ "qoriq-qman1-portals.dtsi"
|
|
+/include/ "qoriq-bman1-portals.dtsi"
|