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375 lines
10 KiB
C
375 lines
10 KiB
C
/*
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* Atheros AR71xx built-in ethernet mac driver
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on Atheros' AG7100 driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __AG71XX_H
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#define __AG71XX_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <asm/ar71xx.h>
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// controller has 2 ports
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#define MAX_AG71XX_DEVS 2
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#define ETH_FCS_LEN 4
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
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#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
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#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
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#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
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#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
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#define AG71XX_TX_FIFO_LEN 2048
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#define AG71XX_TX_MTU_LEN 1536
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#define AG71XX_RX_PKT_RESERVE 64
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#define AG71XX_RX_PKT_SIZE \
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(AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
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#ifndef CONFIG_SYS_RX_ETH_BUFFER
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#define AG71XX_TX_RING_SIZE 4
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#define AG71XX_RX_RING_SIZE 4
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#else
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#define AG71XX_TX_RING_SIZE CONFIG_SYS_RX_ETH_BUFFER
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#define AG71XX_RX_RING_SIZE CONFIG_SYS_RX_ETH_BUFFER
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#endif
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#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
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#define AG71XX_TX_THRES_WAKEUP \
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(AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
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struct ag71xx_desc {
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u32 data;
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u32 ctrl;
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#define DESC_EMPTY BIT(31)
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#define DESC_MORE BIT(24)
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#define DESC_PKTLEN_M 0xfff
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u32 next;
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u32 pad;
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} __attribute__((aligned(4)));
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struct ag71xx_buf {
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struct sk_buff *skb;
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struct ag71xx_desc *desc;
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dma_addr_t dma_addr;
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u32 pad;
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};
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struct ag71xx_ring {
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struct ag71xx_buf *buf;
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u8 *descs_cpu;
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u8 *descs_dma;
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unsigned int desc_size;
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unsigned int curr;
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unsigned int size;
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};
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struct ag71xx {
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uint32_t mac_base;
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uint32_t mii_ctrl;
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struct eth_device *dev;
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struct ag71xx_ring rx_ring;
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struct ag71xx_ring tx_ring;
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char *phyname;
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u16 phyid;
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u16 phyfixed;
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uint32_t link;
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uint32_t speed;
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int32_t duplex;
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uint32_t macNum;
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uint32_t mii_if;
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};
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void ag71xx_link_adjust(struct ag71xx *ag);
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int ag71xx_phy_connect(struct ag71xx *ag);
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void ag71xx_phy_disconnect(struct ag71xx *ag);
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void ag71xx_phy_start(struct ag71xx *ag);
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void ag71xx_phy_stop(struct ag71xx *ag);
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static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
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{
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return ((desc->ctrl & DESC_EMPTY) != 0);
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}
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static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
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{
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return (desc->ctrl & DESC_PKTLEN_M);
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}
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/* Register offsets */
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#define AG71XX_REG_MAC_CFG1 0x0000
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#define AG71XX_REG_MAC_CFG2 0x0004
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#define AG71XX_REG_MAC_IPG 0x0008
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#define AG71XX_REG_MAC_HDX 0x000c
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#define AG71XX_REG_MAC_MFL 0x0010
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#define AG71XX_REG_MII_CFG 0x0020
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#define AG71XX_REG_MII_CMD 0x0024
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#define AG71XX_REG_MII_ADDR 0x0028
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#define AG71XX_REG_MII_CTRL 0x002c
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#define AG71XX_REG_MII_STATUS 0x0030
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#define AG71XX_REG_MII_IND 0x0034
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#define AG71XX_REG_MAC_IFCTL 0x0038
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#define AG71XX_REG_MAC_ADDR1 0x0040
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#define AG71XX_REG_MAC_ADDR2 0x0044
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#define AG71XX_REG_FIFO_CFG0 0x0048
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#define AG71XX_REG_FIFO_CFG1 0x004c
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#define AG71XX_REG_FIFO_CFG2 0x0050
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#define AG71XX_REG_FIFO_CFG3 0x0054
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#define AG71XX_REG_FIFO_CFG4 0x0058
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#define AG71XX_REG_FIFO_CFG5 0x005c
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#define AG71XX_REG_FIFO_RAM0 0x0060
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#define AG71XX_REG_FIFO_RAM1 0x0064
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#define AG71XX_REG_FIFO_RAM2 0x0068
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#define AG71XX_REG_FIFO_RAM3 0x006c
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#define AG71XX_REG_FIFO_RAM4 0x0070
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#define AG71XX_REG_FIFO_RAM5 0x0074
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#define AG71XX_REG_FIFO_RAM6 0x0078
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#define AG71XX_REG_FIFO_RAM7 0x007c
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#define AG71XX_REG_TX_CTRL 0x0180
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#define AG71XX_REG_TX_DESC 0x0184
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#define AG71XX_REG_TX_STATUS 0x0188
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#define AG71XX_REG_RX_CTRL 0x018c
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#define AG71XX_REG_RX_DESC 0x0190
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#define AG71XX_REG_RX_STATUS 0x0194
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#define AG71XX_REG_INT_ENABLE 0x0198
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#define AG71XX_REG_INT_STATUS 0x019c
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#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
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#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
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#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
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#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
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#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
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#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
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#define MAC_CFG1_LB BIT(8) /* Loopback mode */
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#define MAC_CFG1_SR BIT(31) /* Soft Reset */
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#define MAC_CFG2_FDX BIT(0)
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#define MAC_CFG2_CRC_EN BIT(1)
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#define MAC_CFG2_PAD_CRC_EN BIT(2)
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#define MAC_CFG2_LEN_CHECK BIT(4)
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#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
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#define MAC_CFG2_IF_1000 BIT(9)
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#define MAC_CFG2_IF_10_100 BIT(8)
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#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
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#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
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#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
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#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
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#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
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#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
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| FIFO_CFG0_TXS | FIFO_CFG0_TXF)
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#define FIFO_CFG0_ENABLE_SHIFT 8
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#define FIFO_CFG4_DE BIT(0) /* Drop Event */
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#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
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#define FIFO_CFG4_FC BIT(2) /* False Carrier */
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#define FIFO_CFG4_CE BIT(3) /* Code Error */
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#define FIFO_CFG4_CR BIT(4) /* CRC error */
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#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
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#define FIFO_CFG4_LO BIT(6) /* Length out of range */
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#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
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#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
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#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
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#define FIFO_CFG4_DR BIT(10) /* Dribble */
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#define FIFO_CFG4_LE BIT(11) /* Long Event */
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#define FIFO_CFG4_CF BIT(12) /* Control Frame */
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#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
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#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
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#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
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#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
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#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
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#define FIFO_CFG5_DE BIT(0) /* Drop Event */
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#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
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#define FIFO_CFG5_FC BIT(2) /* False Carrier */
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#define FIFO_CFG5_CE BIT(3) /* Code Error */
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#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
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#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
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#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
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#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
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#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
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#define FIFO_CFG5_DR BIT(9) /* Dribble */
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#define FIFO_CFG5_CF BIT(10) /* Control Frame */
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#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
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#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
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#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
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#define FIFO_CFG5_LE BIT(14) /* Long Event */
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#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
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#define FIFO_CFG5_16 BIT(16) /* unknown */
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#define FIFO_CFG5_17 BIT(17) /* unknown */
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#define FIFO_CFG5_SF BIT(18) /* Short Frame */
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#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
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#define AG71XX_INT_TX_PS BIT(0)
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#define AG71XX_INT_TX_UR BIT(1)
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#define AG71XX_INT_TX_BE BIT(3)
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#define AG71XX_INT_RX_PR BIT(4)
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#define AG71XX_INT_RX_OF BIT(6)
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#define AG71XX_INT_RX_BE BIT(7)
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#define MAC_IFCTL_SPEED BIT(16)
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#define MII_CFG_CLK_DIV_4 0
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#define MII_CFG_CLK_DIV_6 2
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#define MII_CFG_CLK_DIV_8 3
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#define MII_CFG_CLK_DIV_10 4
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#define MII_CFG_CLK_DIV_14 5
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#define MII_CFG_CLK_DIV_20 6
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#define MII_CFG_CLK_DIV_28 7
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#define MII_CFG_RESET BIT(31)
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#define MII_CMD_WRITE 0x0
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#define MII_CMD_READ 0x1
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#define MII_ADDR_SHIFT 8
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#define MII_IND_BUSY BIT(0)
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#define MII_IND_INVALID BIT(2)
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#define TX_CTRL_TXE BIT(0) /* Tx Enable */
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#define TX_STATUS_PS BIT(0) /* Packet Sent */
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#define TX_STATUS_UR BIT(1) /* Tx Underrun */
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#define TX_STATUS_BE BIT(3) /* Bus Error */
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#define RX_CTRL_RXE BIT(0) /* Rx Enable */
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#define RX_STATUS_PR BIT(0) /* Packet Received */
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#define RX_STATUS_OF BIT(2) /* Rx Overflow */
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#define RX_STATUS_BE BIT(3) /* Bus Error */
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#define MII_CTRL_IF_MASK 3
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#define MII_CTRL_SPEED_SHIFT 4
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#define MII_CTRL_SPEED_MASK 3
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#define MII_CTRL_SPEED_10 0
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#define MII_CTRL_SPEED_100 1
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#define MII_CTRL_SPEED_1000 2
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static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
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{
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__raw_writel(value, ag->mac_base + reg);
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/* flush write */
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(void) __raw_readl(ag->mac_base + reg);
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}
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static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
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{
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return __raw_readl(ag->mac_base + reg);
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}
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static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
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{
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uint32_t r;
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r = ag->mac_base + reg;
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__raw_writel(__raw_readl(r) | mask, r);
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/* flush write */
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(void)__raw_readl(r);
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}
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static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
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{
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uint32_t r;
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r = ag->mac_base + reg;
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__raw_writel(__raw_readl(r) & ~mask, r);
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/* flush write */
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(void) __raw_readl(r);
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}
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static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
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{
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ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
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}
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static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
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{
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ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
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}
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static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
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{
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__raw_writel(value, ag->mii_ctrl);
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/* flush write */
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__raw_readl(ag->mii_ctrl);
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}
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static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
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{
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return __raw_readl(ag->mii_ctrl);
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}
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static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
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unsigned int mii_if)
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{
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u32 t;
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t = ag71xx_mii_ctrl_rr(ag);
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t &= ~(MII_CTRL_IF_MASK);
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t |= (mii_if & MII_CTRL_IF_MASK);
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ag71xx_mii_ctrl_wr(ag, t);
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}
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static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
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unsigned int speed)
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{
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u32 t;
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t = ag71xx_mii_ctrl_rr(ag);
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t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
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t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
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ag71xx_mii_ctrl_wr(ag, t);
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}
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#ifdef CONFIG_AG71XX_AR8216_SUPPORT
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void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
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int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
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int pktlen);
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static inline int ag71xx_has_ar8216(struct ag71xx *ag)
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{
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return ag71xx_get_pdata(ag)->has_ar8216;
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}
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#else
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static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
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struct sk_buff *skb)
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{
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}
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static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
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struct sk_buff *skb,
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int pktlen)
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{
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return 0;
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}
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static inline int ag71xx_has_ar8216(struct ag71xx *ag)
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{
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return 0;
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}
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#endif
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#endif /* _AG71XX_H */
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