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178 lines
4.5 KiB
C
178 lines
4.5 KiB
C
/*
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* (C) Copyright 2010
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* Michael Kurz <michi.kurz@googlemail.com>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <config.h>
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#include <asm/ar71xx.h>
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#define REG_SIZE 4
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/* === END OF CONFIG === */
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/* register offset */
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#define OFS_RCV_BUFFER (0*REG_SIZE)
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#define OFS_TRANS_HOLD (0*REG_SIZE)
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#define OFS_SEND_BUFFER (0*REG_SIZE)
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#define OFS_INTR_ENABLE (1*REG_SIZE)
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#define OFS_INTR_ID (2*REG_SIZE)
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#define OFS_DATA_FORMAT (3*REG_SIZE)
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#define OFS_LINE_CONTROL (3*REG_SIZE)
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#define OFS_MODEM_CONTROL (4*REG_SIZE)
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#define OFS_RS232_OUTPUT (4*REG_SIZE)
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#define OFS_LINE_STATUS (5*REG_SIZE)
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#define OFS_MODEM_STATUS (6*REG_SIZE)
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#define OFS_RS232_INPUT (6*REG_SIZE)
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#define OFS_SCRATCH_PAD (7*REG_SIZE)
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#define OFS_DIVISOR_LSB (0*REG_SIZE)
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#define OFS_DIVISOR_MSB (1*REG_SIZE)
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#define UART16550_READ(y) readl(KSEG1ADDR(AR71XX_UART_BASE+y))
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#define UART16550_WRITE(x, z) writel(z, KSEG1ADDR((AR71XX_UART_BASE+x)))
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void
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ar71xx_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq)
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{
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#ifndef CONFIG_AR91XX
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u32 pll, pll_div, cpu_div, ahb_div, ddr_div, freq;
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pll = readl(KSEG1ADDR(AR71XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
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pll_div =
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((pll & AR71XX_PLL_DIV_MASK) >> AR71XX_PLL_DIV_SHIFT) + 1;
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cpu_div =
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((pll & AR71XX_CPU_DIV_MASK) >> AR71XX_CPU_DIV_SHIFT) + 1;
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ddr_div =
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((pll & AR71XX_DDR_DIV_MASK) >> AR71XX_DDR_DIV_SHIFT) + 1;
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ahb_div =
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(((pll & AR71XX_AHB_DIV_MASK) >> AR71XX_AHB_DIV_SHIFT) + 1)*2;
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freq = pll_div * 40000000;
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if (cpu_freq)
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*cpu_freq = freq/cpu_div;
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if (ddr_freq)
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*ddr_freq = freq/ddr_div;
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if (ahb_freq)
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*ahb_freq = (freq/cpu_div)/ahb_div;
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#else
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u32 pll, pll_div, ahb_div, ddr_div, freq;
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pll = readl(KSEG1ADDR(AR91XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
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pll_div =
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((pll & AR91XX_PLL_DIV_MASK) >> AR91XX_PLL_DIV_SHIFT);
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ddr_div =
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((pll & AR91XX_DDR_DIV_MASK) >> AR91XX_DDR_DIV_SHIFT) + 1;
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ahb_div =
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(((pll & AR91XX_AHB_DIV_MASK) >> AR91XX_AHB_DIV_SHIFT) + 1)*2;
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freq = pll_div * 5000000;
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if (cpu_freq)
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*cpu_freq = freq;
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if (ddr_freq)
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*ddr_freq = freq/ddr_div;
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if (ahb_freq)
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*ahb_freq = freq/ahb_div;
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#endif
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}
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int serial_init(void)
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{
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u32 div;
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u32 ahb_freq = 100000000;
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ar71xx_sys_frequency (0, 0, &ahb_freq);
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div = ahb_freq/(16 * CONFIG_BAUDRATE);
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// enable uart pins
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#ifndef CONFIG_AR91XX
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writel(AR71XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
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#else
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writel(AR91XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
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#endif
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/* set DIAB bit */
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UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
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/* set divisor */
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UART16550_WRITE(OFS_DIVISOR_LSB, (div & 0xff));
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UART16550_WRITE(OFS_DIVISOR_MSB, ((div >> 8) & 0xff));
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/* clear DIAB bit*/
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UART16550_WRITE(OFS_LINE_CONTROL, 0x00);
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/* set data format */
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UART16550_WRITE(OFS_DATA_FORMAT, 0x3);
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UART16550_WRITE(OFS_INTR_ENABLE, 0);
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return 0;
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}
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int serial_tstc (void)
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{
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return(UART16550_READ(OFS_LINE_STATUS) & 0x1);
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}
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int serial_getc(void)
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{
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while(!serial_tstc());
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return UART16550_READ(OFS_RCV_BUFFER);
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}
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void serial_putc(const char byte)
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{
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if (byte == '\n') serial_putc ('\r');
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while (((UART16550_READ(OFS_LINE_STATUS)) & 0x20) == 0x0);
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UART16550_WRITE(OFS_SEND_BUFFER, byte);
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}
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void serial_setbrg (void)
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{
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}
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void serial_puts (const char *s)
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{
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while (*s)
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{
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serial_putc (*s++);
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}
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}
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