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48 lines
1.4 KiB
Diff
48 lines
1.4 KiB
Diff
From eb8d7fbba907df0a51e504930c00b2c9ec837b54 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 22 Mar 2013 19:25:59 +0100
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Subject: [PATCH 100/121] MIPS: ralink: fix RT305x clock setup
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Add a few missing clocks and remove the unused sys clock.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/rt305x.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -125,6 +125,7 @@ void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
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u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
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+ int wmac_20mhz = 0;
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if (soc_is_rt305x() || soc_is_rt3350()) {
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t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
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@@ -176,11 +177,24 @@ void __init ralink_clk_init(void)
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BUG();
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}
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+ if (soc_is_rt3352() || soc_is_rt5350()) {
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+ u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
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+ if ((val & RT3352_CLKCFG0_XTAL_SEL) == 0)
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+ wmac_20mhz = 1;
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+ }
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+
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000100.timer", wdt_rate);
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+ ralink_clk_add("10000120.watchdog", wdt_rate);
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ralink_clk_add("10000500.uart", uart_rate);
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ralink_clk_add("10000c00.uartlite", uart_rate);
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+ ralink_clk_add("10100000.ethernet", sys_rate);
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+
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+ if (wmac_20mhz)
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+ ralink_clk_add("10180000.wmac", 20000000);
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+ else
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+ ralink_clk_add("10180000.wmac", 40000000);
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}
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void __init ralink_of_remap(void)
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