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129 lines
5.6 KiB
Diff
129 lines
5.6 KiB
Diff
From c5a5706b8a86660505ef0dc863a85596437ca49b Mon Sep 17 00:00:00 2001
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From: Robin Gong <yibin.gong@nxp.com>
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Date: Wed, 30 Aug 2017 18:51:16 +0800
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Subject: [PATCH] MLK-16327-1: dma: fsl-edma-v3: make exclusive channel name
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for all edma channels
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Since there are multi edmav3 instances on i.mx8, every edma channel name
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is better unique.But so far, all edma channel name is 'edma-channel(id)-
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tx',thus some edma channels which share the same channel id but different
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edma instance will show the same channel name in kernel and this is not
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friendly to debug in kernel.
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Now the edma channel name(interrupt-names property) is define in dts
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as below:
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"edmaX-chanX-Xx"
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| | |---> receive/transmit, r or t
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| |---> channel id, the max number is 32
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|---> edma controller instance, 0, 1, 2,..etc
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and get below correct name with 'cat /proc/interrupts':
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43: 0 0 0 0 GICv3 466 Level edma0-chan8-rx
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44: 0 0 0 0 GICv3 467 Level edma0-chan9-tx
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45: 79 0 0 0 GICv3 468 Level edma0-chan10-rx
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46: 311 0 0 0 GICv3 469 Level edma0-chan11-tx
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47: 0 0 0 0 GICv3 470 Level edma0-chan12-rx
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48: 0 0 0 0 GICv3 471 Level edma0-chan13-tx
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49: 0 0 0 0 GICv3 472 Level edma0-chan14-rx
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50: 0 0 0 0 GICv3 473 Level edma0-chan15-tx
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51: 0 0 0 0 GICv3 406 Level edma2-chan0-tx
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52: 0 0 0 0 GICv3 407 Level edma2-chan1-tx
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53: 0 0 0 0 GICv3 408 Level edma2-chan2-tx
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54: 0 0 0 0 GICv3 409 Level edma2-chan3-tx
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55: 0 0 0 0 GICv3 410 Level edma2-chan4-tx
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56: 0 0 0 0 GICv3 411 Level edma2-chan5-tx
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57: 0 0 0 0 GICv3 442 Level edma2-chan6-rx, edma2-chan7-tx
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Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
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(cherry picked from commit af8e197a92c9c024ec4fbfcf543d744e81748773)
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---
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.../devicetree/bindings/dma/fsl-edma-v3.txt | 12 +++++---
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drivers/dma/fsl-edma-v3.c | 35 ++++++++++++++++++++--
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2 files changed, 41 insertions(+), 6 deletions(-)
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--- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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+++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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@@ -12,8 +12,12 @@ Required properties:
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- reg : Specifies base physical address(s) and size of the eDMA channel registers.
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Each eDMA channel has separated register's address and size.
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- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
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-- interrupt-names : Should contain:
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- "edma-chan12-tx" - the channel12 transmission interrupt
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+- interrupt-names : Should contain below template:
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+ "edmaX-chanX-Xx"
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+ | | |---> receive/transmit, r or t
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+ | |---> channel id, the max number is 32
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+ |---> edma controller instance, 0, 1, 2,..etc
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+
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- #dma-cells : Must be <3>.
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The 1st cell specifies the channel ID.
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The 2nd cell specifies the channel priority.
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@@ -40,8 +44,8 @@ edma0: dma-controller@40018000 {
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<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "edma-chan12-tx", "edma-chan13-tx",
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- "edma-chan14-tx", "edma-chan15-tx";
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+ interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx",
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+ "edma0-chan14-rx", "edma0-chan15-tx";
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status = "okay";
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};
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--- a/drivers/dma/fsl-edma-v3.c
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+++ b/drivers/dma/fsl-edma-v3.c
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@@ -107,6 +107,10 @@
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#define ARGS_REMOTE BIT(1)
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#define ARGS_DFIFO BIT(2)
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+/* channel name template define in dts */
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+#define CHAN_PREFIX "edma0-chan"
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+#define CHAN_POSFIX "-tx"
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+
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struct fsl_edma3_hw_tcd {
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__le32 saddr;
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__le16 soff;
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@@ -806,7 +810,10 @@ static int fsl_edma3_probe(struct platfo
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INIT_LIST_HEAD(&fsl_edma3->dma_dev.channels);
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for (i = 0; i < fsl_edma3->n_chans; i++) {
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struct fsl_edma3_chan *fsl_chan = &fsl_edma3->chans[i];
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- char *txirq_name = fsl_chan->txirq_name;
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+ const char *txirq_name = fsl_chan->txirq_name;
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+ char chanid[3], id_len = 0;
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+ char *p = chanid;
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+ unsigned long val;
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fsl_chan->edma3 = fsl_edma3;
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/* Get per channel membase */
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@@ -819,7 +826,31 @@ static int fsl_edma3_probe(struct platfo
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* channel0:0x10000, channel1:0x20000... total 32 channels
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*/
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fsl_chan->hw_chanid = (res->start >> 16) & 0x1f;
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- sprintf(txirq_name, "edma-chan%d-tx", fsl_chan->hw_chanid);
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+
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+ ret = of_property_read_string_index(np, "interrupt-names", i,
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+ &txirq_name);
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+ if (ret) {
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+ dev_err(&pdev->dev, "read interrupt-names fail.\n");
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+ return ret;
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+ }
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+ /* Get channel id length from dts, one-digit or double-digit */
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+ id_len = strlen(txirq_name) - strlen(CHAN_PREFIX) -
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+ strlen(CHAN_POSFIX);
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+ if (id_len > 2) {
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+ dev_err(&pdev->dev, "%s is edmaX-chanX-tx in dts?\n",
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+ res->name);
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+ return -EINVAL;
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+ }
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+ /* Grab channel id from txirq_name */
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+ strncpy(p, txirq_name + strlen(CHAN_PREFIX), id_len);
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+ *(p + id_len) = '\0';
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+
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+ /* check if the channel id match well with hw_chanid */
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+ ret = kstrtoul(chanid, 0, &val);
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+ if (ret || val != fsl_chan->hw_chanid) {
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+ dev_err(&pdev->dev, "%s,wrong id?\n", txirq_name);
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+ return -EINVAL;
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+ }
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/* request channel irq */
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fsl_chan->txirq = platform_get_irq_byname(pdev, txirq_name);
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