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52 lines
1.3 KiB
Diff
52 lines
1.3 KiB
Diff
From 3dc3a4c6ac9e8a0940a9974b8fe2da7641bfa3dd Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Thu, 22 Aug 2019 12:47:12 +0300
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Subject: [PATCH] arm64: dts: LS1028a-rdb: use Ethernet PHY interrupt
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Use the PHY interrupt wired to GPIO pins as part of MDIO WA performance
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impact mitigation.
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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@@ -202,6 +202,8 @@
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#size-cells = <0>;
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sgmii_phy0: ethernet-phy@2 {
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reg = <0x2>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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};
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@@ -213,18 +215,26 @@
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&enetc_mdio_pf3 {
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qsgmii_phy1: ethernet-phy@4 {
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reg = <0x10>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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qsgmii_phy2: ethernet-phy@5 {
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reg = <0x11>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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qsgmii_phy3: ethernet-phy@6 {
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reg = <0x12>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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qsgmii_phy4: ethernet-phy@7 {
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reg = <0x13>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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