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356 lines
7.7 KiB
Diff
356 lines
7.7 KiB
Diff
From 0c767bcfe1b4d940f2889820f12d278cbba764b5 Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Tue, 27 Aug 2019 15:12:00 +0300
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Subject: [PATCH] arm64: dts: ls1028a: define networking options for QDS
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Defines connectivity for a few serdes protocol combinations (85xx, 65xx,
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13xx, 9999, 7777).
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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---
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.../boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi | 20 ++++++++
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.../boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi | 20 ++++++++
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.../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi | 56 ++++++++++++++++++++
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.../boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi | 19 +++++++
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.../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi | 60 ++++++++++++++++++++++
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.../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi | 48 +++++++++++++++++
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.../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi | 44 ++++++++++++++++
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arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 27 ++++++++++
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8 files changed, 294 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-1xxx.dtsi
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@@ -0,0 +1,20 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree Include file for LS1028A QDS board, serdes 1xxx
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+ *
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+ * Copyright 2019 NXP
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+ *
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+ */
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+
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+&mdio_slot1 {
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+ slot1_sgmii: ethernet-phy@2 {
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+ /* AQR112 */
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+ reg = <0x2>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+};
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+
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+&enetc_port0 {
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+ phy-handle = <&slot1_sgmii>;
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+ phy-connection-type = "usxgmii";
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-6xxx.dtsi
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@@ -0,0 +1,20 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree Include file for LS1028A QDS board, serdes 6xxx
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+ *
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+ * Copyright 2019 NXP
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+ *
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+ */
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+
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+&mdio_slot1 {
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+ slot1_sgmii: ethernet-phy@2 {
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+ /* AQR112 */
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+ reg = <0x2>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+};
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+
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+&enetc_port0 {
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+ phy-handle = <&slot1_sgmii>;
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+ phy-connection-type = "2500base-x";
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
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@@ -0,0 +1,56 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree Include file for LS1028A QDS board, serdes 9999
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+ *
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+ * Copyright 2019 NXP
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+ *
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+ */
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+
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+&mdio_slot1 {
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+ /* two ports on AQR412 */
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+ slot1_sxgmii2: ethernet-phy@2 {
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+ reg = <0x2>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+ slot1_sxgmii3: ethernet-phy@3 {
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+ reg = <0x3>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+};
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+
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+&mdio_slot2 {
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+ slot2_sxgmii0: ethernet-phy@2 {
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+ /* AQR112 */
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+ reg = <0x2>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+};
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+
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+&mdio_slot3 {
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+ slot3_sxgmii0: ethernet-phy@2 {
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+ /* AQR112 */
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+ reg = <0x2>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+};
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+
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+/* l2switch ports */
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+&switch_port0 {
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+ phy-handle = <&slot1_sxgmii2>;
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+ phy-connection-type = "2500base-x";
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+};
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+
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+&switch_port1 {
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+ phy-handle = <&slot2_sxgmii0>;
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+ phy-connection-type = "2500base-x";
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+};
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+
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+&switch_port2 {
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+ phy-handle = <&slot3_sxgmii0>;
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+ phy-connection-type = "2500base-x";
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+};
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+
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+&switch_port3 {
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+ phy-handle = <&slot1_sxgmii3>;
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+ phy-connection-type = "2500base-x";
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-8xxx.dtsi
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@@ -0,0 +1,19 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree Include file for LS1028A QDS board, serdes 8xxx
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+ *
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+ * Copyright 2019 NXP
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+ *
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+ */
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+
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+&mdio_slot1 {
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+ slot1_sgmii: ethernet-phy@1c {
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+ /* 1st port on VSC8234 */
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+ reg = <0x1c>;
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+ };
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+};
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+
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+&enetc_port0 {
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+ phy-handle = <&slot1_sgmii>;
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+ phy-connection-type = "sgmii";
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
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@@ -0,0 +1,60 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree Include file for LS1028A QDS board, serdes 9999
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+ *
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+ * Copyright 2019 NXP
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+ *
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+ */
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+
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+&mdio_slot1 {
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+ /* VSC8234 */
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+ slot1_sgmii0: ethernet-phy@1c {
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+ reg = <0x1c>;
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+ };
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+ slot1_sgmii1: ethernet-phy@1d {
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+ reg = <0x1d>;
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+ };
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+ slot1_sgmii2: ethernet-phy@1e {
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+ reg = <0x1e>;
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+ };
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+ slot1_sgmii3: ethernet-phy@1f {
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+ reg = <0x1f>;
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+ };
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+};
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+
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+&mdio_slot2 {
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+ /* VSC8234 */
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+ slot2_sgmii0: ethernet-phy@1c {
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+ reg = <0x1c>;
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+ };
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+ slot2_sgmii1: ethernet-phy@1d {
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+ reg = <0x1d>;
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+ };
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+ slot2_sgmii2: ethernet-phy@1e {
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+ reg = <0x1e>;
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+ };
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+ slot2_sgmii3: ethernet-phy@1f {
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+ reg = <0x1f>;
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+ };
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+};
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+
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+/* l2switch ports */
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+&switch_port0 {
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+ phy-handle = <&slot1_sgmii0>;
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+ phy-connection-type = "sgmii";
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+};
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+
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+&switch_port1 {
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+ phy-handle = <&slot2_sgmii0>;
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+ phy-connection-type = "sgmii";
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+};
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+
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+&switch_port2 {
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+ phy-handle = <&slot1_sgmii2>;
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+ phy-connection-type = "sgmii";
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+};
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+
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+&switch_port3 {
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+ phy-handle = <&slot1_sgmii3>;
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+ phy-connection-type = "sgmii";
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
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@@ -0,0 +1,48 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree Include file for LS1028A QDS board, serdes x3xx
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+ *
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+ * Copyright 2019 NXP
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+ *
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+ */
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+
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+&mdio_slot2 {
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+ /* 4 ports on AQR412 */
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+ slot2_qsgmii0: ethernet-phy@0 {
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+ reg = <0x0>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+ slot2_qsgmii1: ethernet-phy@1 {
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+ reg = <0x1>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+ slot2_qsgmii2: ethernet-phy@2 {
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+ reg = <0x2>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+ slot2_qsgmii3: ethernet-phy@3 {
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+ reg = <0x3>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ };
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+};
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+
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+/* l2switch ports */
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+&switch_port0 {
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+ phy-handle = <&slot2_qsgmii0>;
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+ phy-connection-type = "usxgmii";
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+};
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+
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+&switch_port1 {
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+ phy-handle = <&slot2_qsgmii1>;
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+ phy-connection-type = "usxgmii";
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+};
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+
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+&switch_port2 {
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+ phy-handle = <&slot2_qsgmii2>;
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+ phy-connection-type = "usxgmii";
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+};
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+
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+&switch_port3 {
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+ phy-handle = <&slot2_qsgmii3>;
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+ phy-connection-type = "usxgmii";
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
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@@ -0,0 +1,44 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Device Tree Include file for LS1028A QDS board, serdes x5xx
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+ *
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+ * Copyright 2019 NXP
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+ *
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+ */
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+
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+&mdio_slot2 {
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+ /* 4 ports on VSC8514 */
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+ slot2_qsgmii0: ethernet-phy@8 {
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+ reg = <0x8>;
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+ };
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+ slot2_qsgmii1: ethernet-phy@9 {
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+ reg = <0x9>;
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+ };
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+ slot2_qsgmii2: ethernet-phy@a {
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+ reg = <0xa>;
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+ };
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+ slot2_qsgmii3: ethernet-phy@b {
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+ reg = <0xb>;
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+ };
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+};
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+
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+/* l2switch ports */
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+&switch_port0 {
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+ phy-handle = <&slot2_qsgmii0>;
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+ phy-connection-type = "qsgmii";
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+};
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+
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+&switch_port1 {
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+ phy-handle = <&slot2_qsgmii1>;
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+ phy-connection-type = "qsgmii";
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+};
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+
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+&switch_port2 {
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+ phy-handle = <&slot2_qsgmii2>;
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+ phy-connection-type = "qsgmii";
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+};
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+
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+&switch_port3 {
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+ phy-handle = <&slot2_qsgmii3>;
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+ phy-connection-type = "qsgmii";
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+};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
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@@ -104,6 +104,30 @@
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reg = <5>;
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};
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};
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+
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+ mdio_slot1: mdio@4 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <4>;
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+ };
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+
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+ mdio_slot2: mdio@5 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <5>;
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+ };
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+
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+ mdio_slot3: mdio@6 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <6>;
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+ };
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+
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+ mdio_slot4: mdio@7 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <7>;
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+ };
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};
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};
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@@ -259,3 +283,6 @@
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edp_num_lanes = <0x4>;
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status = "okay";
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};
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+
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+#include "fsl-ls1028a-qds-8xxx.dtsi"
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+#include "fsl-ls1028a-qds-x5xx.dtsi"
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