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621 lines
16 KiB
Diff
621 lines
16 KiB
Diff
From 90be3cb4f1a45b8be4a4ec264cd66c2f8e893fcb Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Fri, 24 Jun 2016 22:18:25 +0200
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Subject: [PATCH 11/16] pinctrl: add a pincontrol driver for BCM6368
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Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32
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GPIOs onto alternative functions. Not all are documented.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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drivers/pinctrl/bcm63xx/Kconfig | 15 +
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drivers/pinctrl/bcm63xx/Makefile | 1 +
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drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c | 573 ++++++++++++++++++++++++++++++
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3 files changed, 589 insertions(+)
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create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c
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--- a/drivers/pinctrl/bcm63xx/Kconfig
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+++ b/drivers/pinctrl/bcm63xx/Kconfig
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@@ -30,3 +30,18 @@ config PINCTRL_BCM6362
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select PINCONF
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select PINCTRL_BCM63XX
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select GENERIC_PINCONF
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+
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+config PINCTRL_BCM6368
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+ bool "BCM6368 pincontrol driver" if COMPILE_TEST
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+ select PINMUX
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+ select PINCONF
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+ select PINCTRL_BCM63XX
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+ select GENERIC_PINCONF
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+ select MFD_SYSCON
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+
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+config PINCTRL_BCM63268
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+ bool "BCM63268 pincontrol driver" if COMPILE_TEST
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+ select PINMUX
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+ select PINCONF
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+ select PINCTRL_BCM63XX
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+ select GENERIC_PINCONF
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--- a/drivers/pinctrl/bcm63xx/Makefile
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+++ b/drivers/pinctrl/bcm63xx/Makefile
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@@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl
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obj-$(CONFIG_PINCTRL_BCM6348) += pinctrl-bcm6348.o
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obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o
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obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
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+obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
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--- /dev/null
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+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c
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@@ -0,0 +1,573 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
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+ */
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+
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+#include <linux/bitops.h>
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+#include <linux/kernel.h>
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+#include <linux/gpio.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/of_gpio.h>
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+#include <linux/pinctrl/pinconf.h>
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+#include <linux/pinctrl/pinconf-generic.h>
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+#include <linux/pinctrl/pinmux.h>
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+#include <linux/pinctrl/machine.h>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+#include <linux/slab.h>
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+#include <linux/spinlock.h>
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+
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+#include "../core.h"
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+#include "../pinctrl-utils.h"
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+
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+#include "pinctrl-bcm63xx.h"
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+
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+#define BCM6368_NGPIO 38
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+
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+#define BCM6368_BASEMODE_MASK 0x7
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+#define BCM6368_BASEMODE_GPIO 0x0
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+#define BCM6368_BASEMODE_UART1 0x1
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+
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+struct bcm6368_pingroup {
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+ const char *name;
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+ const unsigned * const pins;
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+ const unsigned num_pins;
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+};
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+
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+struct bcm6368_function {
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+ const char *name;
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+ const char * const *groups;
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+ const unsigned num_groups;
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+
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+ unsigned dir_out:16;
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+ unsigned basemode:3;
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+};
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+
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+struct bcm6368_pinctrl {
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+ struct pinctrl_dev *pctldev;
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+ struct pinctrl_desc desc;
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+
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+ void __iomem *mode;
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+ struct regmap_field *overlay;
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+
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+ /* register access lock */
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+ spinlock_t lock;
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+
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+ struct gpio_chip gpio[2];
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+};
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+
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+#define BCM6368_BASEMODE_PIN(a, b) \
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+ { \
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+ .number = a, \
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+ .name = b, \
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+ .drv_data = (void *)true \
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+ }
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+
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+static const struct pinctrl_pin_desc bcm6368_pins[] = {
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+ PINCTRL_PIN(0, "gpio0"),
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+ PINCTRL_PIN(1, "gpio1"),
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+ PINCTRL_PIN(2, "gpio2"),
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+ PINCTRL_PIN(3, "gpio3"),
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+ PINCTRL_PIN(4, "gpio4"),
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+ PINCTRL_PIN(5, "gpio5"),
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+ PINCTRL_PIN(6, "gpio6"),
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+ PINCTRL_PIN(7, "gpio7"),
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+ PINCTRL_PIN(8, "gpio8"),
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+ PINCTRL_PIN(9, "gpio9"),
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+ PINCTRL_PIN(10, "gpio10"),
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+ PINCTRL_PIN(11, "gpio11"),
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+ PINCTRL_PIN(12, "gpio12"),
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+ PINCTRL_PIN(13, "gpio13"),
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+ PINCTRL_PIN(14, "gpio14"),
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+ PINCTRL_PIN(15, "gpio15"),
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+ PINCTRL_PIN(16, "gpio16"),
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+ PINCTRL_PIN(17, "gpio17"),
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+ PINCTRL_PIN(18, "gpio18"),
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+ PINCTRL_PIN(19, "gpio19"),
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+ PINCTRL_PIN(20, "gpio20"),
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+ PINCTRL_PIN(21, "gpio21"),
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+ PINCTRL_PIN(22, "gpio22"),
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+ PINCTRL_PIN(23, "gpio23"),
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+ PINCTRL_PIN(24, "gpio24"),
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+ PINCTRL_PIN(25, "gpio25"),
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+ PINCTRL_PIN(26, "gpio26"),
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+ PINCTRL_PIN(27, "gpio27"),
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+ PINCTRL_PIN(28, "gpio28"),
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+ PINCTRL_PIN(29, "gpio29"),
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+ BCM6368_BASEMODE_PIN(30, "gpio30"),
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+ BCM6368_BASEMODE_PIN(31, "gpio31"),
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+ BCM6368_BASEMODE_PIN(32, "gpio32"),
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+ BCM6368_BASEMODE_PIN(33, "gpio33"),
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+ PINCTRL_PIN(34, "gpio34"),
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+ PINCTRL_PIN(35, "gpio35"),
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+ PINCTRL_PIN(36, "gpio36"),
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+ PINCTRL_PIN(37, "gpio37"),
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+};
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+
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+static unsigned gpio0_pins[] = { 0 };
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+static unsigned gpio1_pins[] = { 1 };
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+static unsigned gpio2_pins[] = { 2 };
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+static unsigned gpio3_pins[] = { 3 };
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+static unsigned gpio4_pins[] = { 4 };
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+static unsigned gpio5_pins[] = { 5 };
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+static unsigned gpio6_pins[] = { 6 };
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+static unsigned gpio7_pins[] = { 7 };
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+static unsigned gpio8_pins[] = { 8 };
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+static unsigned gpio9_pins[] = { 9 };
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+static unsigned gpio10_pins[] = { 10 };
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+static unsigned gpio11_pins[] = { 11 };
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+static unsigned gpio12_pins[] = { 12 };
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+static unsigned gpio13_pins[] = { 13 };
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+static unsigned gpio14_pins[] = { 14 };
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+static unsigned gpio15_pins[] = { 15 };
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+static unsigned gpio16_pins[] = { 16 };
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+static unsigned gpio17_pins[] = { 17 };
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+static unsigned gpio18_pins[] = { 18 };
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+static unsigned gpio19_pins[] = { 19 };
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+static unsigned gpio20_pins[] = { 20 };
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+static unsigned gpio21_pins[] = { 21 };
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+static unsigned gpio22_pins[] = { 22 };
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+static unsigned gpio23_pins[] = { 23 };
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+static unsigned gpio24_pins[] = { 24 };
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+static unsigned gpio25_pins[] = { 25 };
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+static unsigned gpio26_pins[] = { 26 };
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+static unsigned gpio27_pins[] = { 27 };
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+static unsigned gpio28_pins[] = { 28 };
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+static unsigned gpio29_pins[] = { 29 };
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+static unsigned gpio30_pins[] = { 30 };
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+static unsigned gpio31_pins[] = { 31 };
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+static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
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+
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+#define BCM6368_GROUP(n) \
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+ { \
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+ .name = #n, \
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+ .pins = n##_pins, \
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+ .num_pins = ARRAY_SIZE(n##_pins), \
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+ }
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+
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+static struct bcm6368_pingroup bcm6368_groups[] = {
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+ BCM6368_GROUP(gpio0),
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+ BCM6368_GROUP(gpio1),
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+ BCM6368_GROUP(gpio2),
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+ BCM6368_GROUP(gpio3),
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+ BCM6368_GROUP(gpio4),
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+ BCM6368_GROUP(gpio5),
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+ BCM6368_GROUP(gpio6),
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+ BCM6368_GROUP(gpio7),
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+ BCM6368_GROUP(gpio8),
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+ BCM6368_GROUP(gpio9),
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+ BCM6368_GROUP(gpio10),
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+ BCM6368_GROUP(gpio11),
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+ BCM6368_GROUP(gpio12),
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+ BCM6368_GROUP(gpio13),
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+ BCM6368_GROUP(gpio14),
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+ BCM6368_GROUP(gpio15),
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+ BCM6368_GROUP(gpio16),
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+ BCM6368_GROUP(gpio17),
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+ BCM6368_GROUP(gpio18),
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+ BCM6368_GROUP(gpio19),
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+ BCM6368_GROUP(gpio20),
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+ BCM6368_GROUP(gpio21),
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+ BCM6368_GROUP(gpio22),
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+ BCM6368_GROUP(gpio23),
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+ BCM6368_GROUP(gpio24),
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+ BCM6368_GROUP(gpio25),
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+ BCM6368_GROUP(gpio26),
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+ BCM6368_GROUP(gpio27),
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+ BCM6368_GROUP(gpio28),
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+ BCM6368_GROUP(gpio29),
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+ BCM6368_GROUP(gpio30),
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+ BCM6368_GROUP(gpio31),
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+ BCM6368_GROUP(uart1_grp),
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+};
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+
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+static const char * const analog_afe_0_groups[] = {
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+ "gpio0",
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+};
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+
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+static const char * const analog_afe_1_groups[] = {
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+ "gpio1",
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+};
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+
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+static const char * const sys_irq_groups[] = {
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+ "gpio2",
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+};
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+
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+static const char * const serial_led_data_groups[] = {
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+ "gpio3",
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+};
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+
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+static const char * const serial_led_clk_groups[] = {
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+ "gpio4",
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+};
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+
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+static const char * const inet_led_groups[] = {
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+ "gpio5",
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+};
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+
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+static const char * const ephy0_led_groups[] = {
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+ "gpio6",
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+};
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+
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+static const char * const ephy1_led_groups[] = {
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+ "gpio7",
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+};
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+
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+static const char * const ephy2_led_groups[] = {
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+ "gpio8",
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+};
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+
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+static const char * const ephy3_led_groups[] = {
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+ "gpio9",
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+};
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+
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+static const char * const robosw_led_data_groups[] = {
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+ "gpio10",
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+};
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+
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+static const char * const robosw_led_clk_groups[] = {
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+ "gpio11",
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+};
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+
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+static const char * const robosw_led0_groups[] = {
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+ "gpio12",
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+};
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+
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+static const char * const robosw_led1_groups[] = {
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+ "gpio13",
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+};
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+
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+static const char * const usb_device_led_groups[] = {
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+ "gpio14",
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+};
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+
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+static const char * const pci_req1_groups[] = {
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+ "gpio16",
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+};
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+
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+static const char * const pci_gnt1_groups[] = {
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+ "gpio17",
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+};
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+
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+static const char * const pci_intb_groups[] = {
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+ "gpio18",
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+};
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+
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+static const char * const pci_req0_groups[] = {
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+ "gpio19",
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+};
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+
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+static const char * const pci_gnt0_groups[] = {
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+ "gpio20",
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+};
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+
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+static const char * const pcmcia_cd1_groups[] = {
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+ "gpio22",
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+};
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+
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+static const char * const pcmcia_cd2_groups[] = {
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+ "gpio23",
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+};
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+
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+static const char * const pcmcia_vs1_groups[] = {
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+ "gpio24",
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+};
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+
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+static const char * const pcmcia_vs2_groups[] = {
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+ "gpio25",
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+};
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+
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+static const char * const ebi_cs2_groups[] = {
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+ "gpio26",
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+};
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+
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+static const char * const ebi_cs3_groups[] = {
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+ "gpio27",
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+};
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+
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+static const char * const spi_cs2_groups[] = {
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+ "gpio28",
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+};
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+
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+static const char * const spi_cs3_groups[] = {
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+ "gpio29",
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+};
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+
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+static const char * const spi_cs4_groups[] = {
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+ "gpio30",
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+};
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+
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+static const char * const spi_cs5_groups[] = {
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+ "gpio31",
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+};
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+
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+static const char * const uart1_groups[] = {
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+ "uart1_grp",
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+};
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+
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+#define BCM6368_FUN(n, out) \
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+ { \
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+ .name = #n, \
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+ .groups = n##_groups, \
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+ .num_groups = ARRAY_SIZE(n##_groups), \
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+ .dir_out = out, \
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+ }
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+
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+#define BCM6368_BASEMODE_FUN(n, val, out) \
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+ { \
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+ .name = #n, \
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+ .groups = n##_groups, \
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+ .num_groups = ARRAY_SIZE(n##_groups), \
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+ .basemode = BCM6368_BASEMODE_##val, \
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+ .dir_out = out, \
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+ }
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+
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+static const struct bcm6368_function bcm6368_funcs[] = {
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+ BCM6368_FUN(analog_afe_0, 1),
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+ BCM6368_FUN(analog_afe_1, 1),
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+ BCM6368_FUN(sys_irq, 1),
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+ BCM6368_FUN(serial_led_data, 1),
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+ BCM6368_FUN(serial_led_clk, 1),
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+ BCM6368_FUN(inet_led, 1),
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+ BCM6368_FUN(ephy0_led, 1),
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+ BCM6368_FUN(ephy1_led, 1),
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+ BCM6368_FUN(ephy2_led, 1),
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+ BCM6368_FUN(ephy3_led, 1),
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+ BCM6368_FUN(robosw_led_data, 1),
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+ BCM6368_FUN(robosw_led_clk, 1),
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+ BCM6368_FUN(robosw_led0, 1),
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+ BCM6368_FUN(robosw_led1, 1),
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+ BCM6368_FUN(usb_device_led, 1),
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+ BCM6368_FUN(pci_req1, 0),
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+ BCM6368_FUN(pci_gnt1, 0),
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+ BCM6368_FUN(pci_intb, 0),
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+ BCM6368_FUN(pci_req0, 0),
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+ BCM6368_FUN(pci_gnt0, 0),
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+ BCM6368_FUN(pcmcia_cd1, 0),
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+ BCM6368_FUN(pcmcia_cd2, 0),
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+ BCM6368_FUN(pcmcia_vs1, 0),
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+ BCM6368_FUN(pcmcia_vs2, 0),
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+ BCM6368_FUN(ebi_cs2, 1),
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+ BCM6368_FUN(ebi_cs3, 1),
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+ BCM6368_FUN(spi_cs2, 1),
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+ BCM6368_FUN(spi_cs3, 1),
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+ BCM6368_FUN(spi_cs4, 1),
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+ BCM6368_FUN(spi_cs5, 1),
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+ BCM6368_BASEMODE_FUN(uart1, UART1, 0x6),
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+};
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+
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+static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
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+{
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+ return ARRAY_SIZE(bcm6368_groups);
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+}
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+
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+static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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+ unsigned group)
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+{
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+ return bcm6368_groups[group].name;
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+}
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+
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+static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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+ unsigned group, const unsigned **pins,
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+ unsigned *num_pins)
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+{
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+ *pins = bcm6368_groups[group].pins;
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+ *num_pins = bcm6368_groups[group].num_pins;
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+
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+ return 0;
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+}
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+
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+static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
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+{
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+ return ARRAY_SIZE(bcm6368_funcs);
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+}
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+
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+static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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+ unsigned selector)
|
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+{
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+ return bcm6368_funcs[selector].name;
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+}
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+
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+static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,
|
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+ unsigned selector,
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+ const char * const **groups,
|
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+ unsigned * const num_groups)
|
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+{
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+ *groups = bcm6368_funcs[selector].groups;
|
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+ *num_groups = bcm6368_funcs[selector].num_groups;
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+
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+ return 0;
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+}
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+
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+static void bcm6368_rmw_mux(struct bcm6368_pinctrl *pctl, void __iomem *reg,
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+ u32 mask, u32 val)
|
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+{
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+ u32 tmp;
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+
|
|
+ tmp = __raw_readl(reg);
|
|
+ tmp &= ~mask;
|
|
+ tmp |= (val & mask);
|
|
+ __raw_writel(tmp, reg);
|
|
+}
|
|
+
|
|
+static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
|
|
+ unsigned selector, unsigned group)
|
|
+{
|
|
+ struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
+ const struct bcm6368_pingroup *grp = &bcm6368_groups[group];
|
|
+ const struct bcm6368_function *fun = &bcm6368_funcs[selector];
|
|
+ unsigned long flags;
|
|
+ int i, pin;
|
|
+
|
|
+ spin_lock_irqsave(&pctl->lock, flags);
|
|
+ if (fun->basemode) {
|
|
+ u32 mask = 0;
|
|
+
|
|
+ for (i = 0; i < grp->num_pins; i++) {
|
|
+ pin = grp->pins[i];
|
|
+ if (pin < 32)
|
|
+ mask |= BIT(pin);
|
|
+ }
|
|
+
|
|
+ bcm6368_rmw_mux(pctl, pctl->mode, mask, 0);
|
|
+ regmap_field_write(pctl->overlay, fun->basemode);
|
|
+ } else {
|
|
+ pin = grp->pins[0];
|
|
+
|
|
+ if (bcm6368_pins[pin].drv_data)
|
|
+ regmap_field_write(pctl->overlay,
|
|
+ BCM6368_BASEMODE_GPIO);
|
|
+
|
|
+ bcm6368_rmw_mux(pctl, pctl->mode, BIT(pin), BIT(pin));
|
|
+ }
|
|
+ spin_unlock_irqrestore(&pctl->lock, flags);
|
|
+
|
|
+ for (pin = 0; pin < grp->num_pins; pin++) {
|
|
+ int hw_gpio = bcm6368_pins[pin].number;
|
|
+ struct gpio_chip *gc = &pctl->gpio[hw_gpio / 32];
|
|
+
|
|
+ if (fun->dir_out & BIT(pin))
|
|
+ gc->direction_output(gc, hw_gpio % 32, 0);
|
|
+ else
|
|
+ gc->direction_input(gc, hw_gpio % 32);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,
|
|
+ struct pinctrl_gpio_range *range,
|
|
+ unsigned offset)
|
|
+{
|
|
+ struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
+ unsigned long flags;
|
|
+
|
|
+ if (offset >= 32 && !bcm6368_pins[offset].drv_data)
|
|
+ return 0;
|
|
+
|
|
+ spin_lock_irqsave(&pctl->lock, flags);
|
|
+ /* disable all functions using this pin */
|
|
+ if (offset < 32)
|
|
+ bcm6368_rmw_mux(pctl, pctl->mode, BIT(offset), 0);
|
|
+
|
|
+ if (bcm6368_pins[offset].drv_data)
|
|
+ regmap_field_write(pctl->overlay, BCM6368_BASEMODE_GPIO);
|
|
+
|
|
+ spin_unlock_irqrestore(&pctl->lock, flags);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct pinctrl_ops bcm6368_pctl_ops = {
|
|
+ .get_groups_count = bcm6368_pinctrl_get_group_count,
|
|
+ .get_group_name = bcm6368_pinctrl_get_group_name,
|
|
+ .get_group_pins = bcm6368_pinctrl_get_group_pins,
|
|
+#ifdef CONFIG_OF
|
|
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
|
|
+ .dt_free_map = pinctrl_utils_free_map,
|
|
+#endif
|
|
+};
|
|
+
|
|
+static struct pinmux_ops bcm6368_pmx_ops = {
|
|
+ .get_functions_count = bcm6368_pinctrl_get_func_count,
|
|
+ .get_function_name = bcm6368_pinctrl_get_func_name,
|
|
+ .get_function_groups = bcm6368_pinctrl_get_groups,
|
|
+ .set_mux = bcm6368_pinctrl_set_mux,
|
|
+ .gpio_request_enable = bcm6368_gpio_request_enable,
|
|
+ .strict = true,
|
|
+};
|
|
+
|
|
+static int bcm6368_pinctrl_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct bcm6368_pinctrl *pctl;
|
|
+ struct resource *res;
|
|
+ void __iomem *mode;
|
|
+ struct regmap *basemode;
|
|
+ struct reg_field overlay = REG_FIELD(0, 0, 3);
|
|
+
|
|
+ if (pdev->dev.of_node)
|
|
+ basemode = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
|
+ "brcm,gpiobasemode");
|
|
+ else
|
|
+ basemode = syscon_regmap_lookup_by_pdevname("syscon.b00000b8");
|
|
+
|
|
+ if (IS_ERR(basemode))
|
|
+ return PTR_ERR(basemode);
|
|
+
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
|
|
+ mode = devm_ioremap_resource(&pdev->dev, res);
|
|
+ if (IS_ERR(mode))
|
|
+ return PTR_ERR(mode);
|
|
+
|
|
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
|
|
+ if (!pctl)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ pctl->overlay = devm_regmap_field_alloc(&pdev->dev, basemode, overlay);
|
|
+ if (IS_ERR(pctl->overlay))
|
|
+ return PTR_ERR(pctl->overlay);
|
|
+
|
|
+ spin_lock_init(&pctl->lock);
|
|
+
|
|
+ pctl->mode = mode;
|
|
+
|
|
+ /* disable all muxes by default */
|
|
+ __raw_writel(0, pctl->mode);
|
|
+
|
|
+ pctl->desc.name = dev_name(&pdev->dev);
|
|
+ pctl->desc.owner = THIS_MODULE;
|
|
+ pctl->desc.pctlops = &bcm6368_pctl_ops;
|
|
+ pctl->desc.pmxops = &bcm6368_pmx_ops;
|
|
+
|
|
+ pctl->desc.npins = ARRAY_SIZE(bcm6368_pins);
|
|
+ pctl->desc.pins = bcm6368_pins;
|
|
+
|
|
+ platform_set_drvdata(pdev, pctl);
|
|
+
|
|
+ pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
|
|
+ pctl->gpio, BCM6368_NGPIO);
|
|
+ if (IS_ERR(pctl->pctldev))
|
|
+ return PTR_ERR(pctl->pctldev);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id bcm6368_pinctrl_match[] = {
|
|
+ { .compatible = "brcm,bcm6368-pinctrl", },
|
|
+ { },
|
|
+};
|
|
+
|
|
+static struct platform_driver bcm6368_pinctrl_driver = {
|
|
+ .probe = bcm6368_pinctrl_probe,
|
|
+ .driver = {
|
|
+ .name = "bcm6368-pinctrl",
|
|
+ .of_match_table = bcm6368_pinctrl_match,
|
|
+ },
|
|
+};
|
|
+
|
|
+builtin_platform_driver(bcm6368_pinctrl_driver);
|