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162 lines
6.1 KiB
Diff
162 lines
6.1 KiB
Diff
From: Russell King <rmk+kernel@armlinux.org.uk>
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Bcc: linux@mail.armlinux.org.uk
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Cc: linux-i2c@vger.kernel.org
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Subject: [PATCH 05/17] i2c: pxa: re-arrange register field definitions
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MIME-Version: 1.0
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Content-Disposition: inline
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Content-Transfer-Encoding: 8bit
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Content-Type: text/plain; charset="utf-8"
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Arrange the register field definitions to be grouped together, rather
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than the Armada-3700 definitions being separated from the rest of the
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definitions.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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---
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drivers/i2c/busses/i2c-pxa.c | 113 ++++++++++++++++-------------------
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1 file changed, 53 insertions(+), 60 deletions(-)
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--- a/drivers/i2c/busses/i2c-pxa.c
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+++ b/drivers/i2c/busses/i2c-pxa.c
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@@ -33,6 +33,56 @@
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#include <linux/platform_data/i2c-pxa.h>
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#include <linux/slab.h>
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+/* I2C register field definitions */
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+#define ICR_START (1 << 0) /* start bit */
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+#define ICR_STOP (1 << 1) /* stop bit */
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+#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
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+#define ICR_TB (1 << 3) /* transfer byte bit */
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+#define ICR_MA (1 << 4) /* master abort */
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+#define ICR_SCLE (1 << 5) /* master clock enable */
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+#define ICR_IUE (1 << 6) /* unit enable */
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+#define ICR_GCD (1 << 7) /* general call disable */
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+#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
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+#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
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+#define ICR_BEIE (1 << 10) /* enable bus error ints */
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+#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
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+#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
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+#define ICR_SADIE (1 << 13) /* slave address detected int enable */
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+#define ICR_UR (1 << 14) /* unit reset */
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+#define ICR_FM (1 << 15) /* fast mode */
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+#define ICR_HS (1 << 16) /* High Speed mode */
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+#define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
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+#define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
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+#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
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+
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+#define ISR_RWM (1 << 0) /* read/write mode */
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+#define ISR_ACKNAK (1 << 1) /* ack/nak status */
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+#define ISR_UB (1 << 2) /* unit busy */
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+#define ISR_IBB (1 << 3) /* bus busy */
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+#define ISR_SSD (1 << 4) /* slave stop detected */
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+#define ISR_ALD (1 << 5) /* arbitration loss detected */
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+#define ISR_ITE (1 << 6) /* tx buffer empty */
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+#define ISR_IRF (1 << 7) /* rx buffer full */
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+#define ISR_GCAD (1 << 8) /* general call address detected */
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+#define ISR_SAD (1 << 9) /* slave address detected */
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+#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
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+
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+#define ILCR_SLV_SHIFT 0
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+#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
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+#define ILCR_FLV_SHIFT 9
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+#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
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+#define ILCR_HLVL_SHIFT 18
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+#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
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+#define ILCR_HLVH_SHIFT 27
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+#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
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+
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+#define IWCR_CNT_SHIFT 0
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+#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
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+#define IWCR_HS_CNT1_SHIFT 5
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+#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
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+#define IWCR_HS_CNT2_SHIFT 10
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+#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
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+
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struct pxa_reg_layout {
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u32 ibmr;
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u32 idbr;
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@@ -53,12 +103,7 @@ enum pxa_i2c_types {
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REGS_A3700,
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};
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-#define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */
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-#define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */
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-
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-/*
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- * I2C registers definitions
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- */
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+/* I2C register layout definitions */
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static struct pxa_reg_layout pxa_reg_layout[] = {
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[REGS_PXA2XX] = {
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.ibmr = 0x00,
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@@ -96,8 +141,8 @@ static struct pxa_reg_layout pxa_reg_lay
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.icr = 0x08,
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.isr = 0x0c,
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.isar = 0x10,
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- .fm = ICR_BUSMODE_FM,
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- .hs = ICR_BUSMODE_HS,
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+ .fm = ICR_A3700_FM,
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+ .hs = ICR_A3700_HS,
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},
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};
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@@ -111,58 +156,6 @@ static const struct platform_device_id i
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};
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MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
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-/*
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- * I2C bit definitions
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- */
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-
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-#define ICR_START (1 << 0) /* start bit */
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-#define ICR_STOP (1 << 1) /* stop bit */
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-#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
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-#define ICR_TB (1 << 3) /* transfer byte bit */
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-#define ICR_MA (1 << 4) /* master abort */
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-#define ICR_SCLE (1 << 5) /* master clock enable */
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-#define ICR_IUE (1 << 6) /* unit enable */
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-#define ICR_GCD (1 << 7) /* general call disable */
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-#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
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-#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
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-#define ICR_BEIE (1 << 10) /* enable bus error ints */
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-#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
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-#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
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-#define ICR_SADIE (1 << 13) /* slave address detected int enable */
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-#define ICR_UR (1 << 14) /* unit reset */
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-#define ICR_FM (1 << 15) /* fast mode */
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-#define ICR_HS (1 << 16) /* High Speed mode */
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-#define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
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-
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-#define ISR_RWM (1 << 0) /* read/write mode */
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-#define ISR_ACKNAK (1 << 1) /* ack/nak status */
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-#define ISR_UB (1 << 2) /* unit busy */
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-#define ISR_IBB (1 << 3) /* bus busy */
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-#define ISR_SSD (1 << 4) /* slave stop detected */
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-#define ISR_ALD (1 << 5) /* arbitration loss detected */
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-#define ISR_ITE (1 << 6) /* tx buffer empty */
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-#define ISR_IRF (1 << 7) /* rx buffer full */
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-#define ISR_GCAD (1 << 8) /* general call address detected */
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-#define ISR_SAD (1 << 9) /* slave address detected */
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-#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
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-
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-/* bit field shift & mask */
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-#define ILCR_SLV_SHIFT 0
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-#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
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-#define ILCR_FLV_SHIFT 9
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-#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
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-#define ILCR_HLVL_SHIFT 18
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-#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
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-#define ILCR_HLVH_SHIFT 27
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-#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
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-
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-#define IWCR_CNT_SHIFT 0
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-#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
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-#define IWCR_HS_CNT1_SHIFT 5
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-#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
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-#define IWCR_HS_CNT2_SHIFT 10
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-#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
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-
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struct pxa_i2c {
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spinlock_t lock;
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wait_queue_head_t wait;
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