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195 lines
7.1 KiB
Diff
195 lines
7.1 KiB
Diff
From 783addfa256e79892f889e95ec5cda34f4e91eb7 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Fri, 9 Dec 2011 20:36:32 +0100
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Subject: [PATCH 24/35] MIPS: ath79: add clock initialization code for AR934X
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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---
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arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++
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2 files changed, 134 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -1,8 +1,11 @@
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/*
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* Atheros AR71XX/AR724X/AR913X common routines
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*
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+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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+ *
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo
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ath79_uart_clk.rate = ath79_ref_clk.rate;
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}
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+static void __init ar934x_clocks_init(void)
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+{
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
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+ ath79_ref_clk.rate = 40 * 1000 * 1000;
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+ else
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+ ath79_ref_clk.rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_NINT_MASK;
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+ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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+ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
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+
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+ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
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+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_NINT_MASK;
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+ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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+ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
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+
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+ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
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+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
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+ ddr_pll /= (1 << out_div);
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+
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+ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
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+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
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+ else
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+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
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+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
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+ else
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+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
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+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
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+ else
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+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
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+ ath79_uart_clk.rate = ath79_ref_clk.rate;
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+}
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+
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void)
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ar913x_clocks_init();
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else if (soc_is_ar933x())
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ar933x_clocks_init();
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+ else if (soc_is_ar934x())
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+ ar934x_clocks_init();
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else
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BUG();
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -151,6 +151,41 @@
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
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+#define AR934X_PLL_CPU_CONFIG_REG 0x00
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+#define AR934X_PLL_DDR_CONFIG_REG 0x04
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
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+
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+#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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+#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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+#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
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+#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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+#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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+#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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+#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
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+#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
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+
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+#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
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+#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
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+#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
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+#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
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+#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
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+#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
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+#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
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+#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
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+
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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+
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/*
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* USB_CONFIG block
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*/
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@@ -186,6 +221,8 @@
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#define AR933X_RESET_REG_RESET_MODULE 0x1c
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#define AR933X_RESET_REG_BOOTSTRAP 0xac
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+#define AR934X_RESET_REG_BOOTSTRAP 0xb0
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+
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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@@ -242,6 +279,22 @@
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
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+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
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+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
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+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
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+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
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+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
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+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
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+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
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+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
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+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
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+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
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+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
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+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
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+
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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