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openwrt/target/linux/ipq40xx/files-5.4/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-...

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// SPDX-License-Identifier: GPL-2.0 OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EZVIZ CS-W3-WD1200G EUP";
compatible = "ezviz,cs-w3-wd1200g-eup";
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_red;
led-running = &led_status_blue;
led-upgrade = &led_status_green;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
reset-delay-us = <5000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_status_red: status_red {
label = "cs-w3-wd1200g-eup:red:status";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
led_status_green: status_green {
label = "cs-w3-wd1200g-eup:green:status";
gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
led_status_blue: status_blue {
label = "cs-w3-wd1200g-eup:blue:status";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@E0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@F0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition9@580000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x00e80000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
};