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461 lines
10 KiB
C
461 lines
10 KiB
C
/*
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* NAND flash driver for the MikroTik RouterBOARD 91x series
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*
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* Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/gpio.h>
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#include <linux/platform_data/rb91x_nand.h>
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#include <linux/version.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#define DRV_DESC "NAND flash driver for the RouterBOARD 91x series"
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#define RB91X_NAND_NRWE BIT(12)
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#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
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BIT(13) | BIT(14) | BIT(15))
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#define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
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#define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
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#define RB91X_NAND_LOW_DATA_MASK 0x1f
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#define RB91X_NAND_HIGH_DATA_MASK 0xe0
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#define RB91X_NAND_HIGH_DATA_SHIFT 8
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struct rb91x_nand_info {
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struct nand_chip chip;
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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struct mtd_info mtd;
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#endif
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struct device *dev;
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int gpio_nce;
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int gpio_ale;
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int gpio_cle;
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int gpio_rdy;
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int gpio_read;
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int gpio_nrw;
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int gpio_nle;
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};
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static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
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{
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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return container_of(mtd, struct rb91x_nand_info, mtd);
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#else
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struct nand_chip *chip = mtd_to_nand(mtd);
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return container_of(chip, struct rb91x_nand_info, chip);
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#endif
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}
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static struct mtd_info *rbinfo_to_mtd(struct rb91x_nand_info *nfc)
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{
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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return &nfc->mtd;
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#else
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return nand_to_mtd(&nfc->chip);
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#endif
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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/*
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* We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
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* will not be able to find the kernel that we load.
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*/
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static struct nand_ecclayout rb91x_nand_ecclayout = {
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.eccbytes = 6,
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.eccpos = { 8, 9, 10, 13, 14, 15 },
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.oobavail = 9,
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.oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
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};
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#else
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static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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switch (section) {
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case 0:
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oobregion->offset = 8;
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oobregion->length = 3;
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return 0;
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case 1:
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oobregion->offset = 13;
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oobregion->length = 3;
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return 0;
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default:
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return -ERANGE;
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}
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}
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static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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switch (section) {
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case 0:
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oobregion->offset = 0;
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oobregion->length = 4;
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return 0;
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case 1:
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oobregion->offset = 4;
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oobregion->length = 1;
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return 0;
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case 2:
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oobregion->offset = 6;
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oobregion->length = 2;
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return 0;
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case 3:
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oobregion->offset = 11;
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oobregion->length = 2;
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return 0;
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default:
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return -ERANGE;
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}
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}
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static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
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.ecc = rb91x_ooblayout_ecc,
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.free = rb91x_ooblayout_free,
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};
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#endif /* < 4.6 */
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static struct mtd_partition rb91x_nand_partitions[] = {
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{
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.name = "booter",
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.offset = 0,
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.size = (256 * 1024),
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.offset = (256 * 1024),
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.size = (4 * 1024 * 1024) - (256 * 1024),
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}, {
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.name = "ubi",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static void rb91x_nand_write(struct rb91x_nand_info *rbni,
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const u8 *buf,
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unsigned len)
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{
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void __iomem *base = ath79_gpio_base;
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u32 oe_reg;
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u32 out_reg;
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u32 out;
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unsigned i;
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/* enable the latch */
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gpio_set_value_cansleep(rbni->gpio_nle, 0);
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* set data lines to output mode */
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__raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
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base + AR71XX_GPIO_REG_OE);
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out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
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for (i = 0; i != len; i++) {
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u32 data;
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data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
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RB91X_NAND_HIGH_DATA_SHIFT;
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data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
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data |= out;
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__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
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/* deactivate WE line */
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data |= RB91X_NAND_NRWE;
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__raw_writel(data, base + AR71XX_GPIO_REG_OUT);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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}
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/* restore registers */
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* disable the latch */
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gpio_set_value_cansleep(rbni->gpio_nle, 1);
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}
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static void rb91x_nand_read(struct rb91x_nand_info *rbni,
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u8 *read_buf,
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unsigned len)
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{
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void __iomem *base = ath79_gpio_base;
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u32 oe_reg;
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u32 out_reg;
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unsigned i;
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/* enable read mode */
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gpio_set_value_cansleep(rbni->gpio_read, 1);
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/* enable latch */
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gpio_set_value_cansleep(rbni->gpio_nle, 0);
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/* save registers */
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oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
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out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* set data lines to input mode */
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__raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
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base + AR71XX_GPIO_REG_OE);
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for (i = 0; i < len; i++) {
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u32 in;
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u8 data;
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/* activate RE line */
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__raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_CLEAR);
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/* read input lines */
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in = __raw_readl(base + AR71XX_GPIO_REG_IN);
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/* deactivate RE line */
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__raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
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data = (in & RB91X_NAND_LOW_DATA_MASK);
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data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
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RB91X_NAND_HIGH_DATA_MASK;
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read_buf[i] = data;
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}
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/* restore registers */
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__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
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__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_OUT);
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/* disable latch */
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gpio_set_value_cansleep(rbni->gpio_nle, 1);
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/* disable read mode */
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gpio_set_value_cansleep(rbni->gpio_read, 0);
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}
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static int rb91x_nand_dev_ready(struct mtd_info *mtd)
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{
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
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return gpio_get_value_cansleep(rbni->gpio_rdy);
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}
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static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
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if (ctrl & NAND_CTRL_CHANGE) {
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gpio_set_value_cansleep(rbni->gpio_cle,
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(ctrl & NAND_CLE) ? 1 : 0);
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gpio_set_value_cansleep(rbni->gpio_ale,
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(ctrl & NAND_ALE) ? 1 : 0);
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gpio_set_value_cansleep(rbni->gpio_nce,
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(ctrl & NAND_NCE) ? 0 : 1);
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}
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if (cmd != NAND_CMD_NONE) {
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u8 t = cmd;
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rb91x_nand_write(rbni, &t, 1);
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}
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}
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static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
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{
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
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u8 data = 0xff;
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rb91x_nand_read(rbni, &data, 1);
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return data;
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}
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static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
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rb91x_nand_read(rbni, buf, len);
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}
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static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
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rb91x_nand_write(rbni, buf, len);
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}
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static int rb91x_nand_gpio_init(struct rb91x_nand_info *info)
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{
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int ret;
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/*
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* Ensure that the LATCH is disabled before initializing
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* control lines.
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*/
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ret = devm_gpio_request_one(info->dev, info->gpio_nle,
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GPIOF_OUT_INIT_HIGH, "LATCH enable");
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if (ret)
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return ret;
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ret = devm_gpio_request_one(info->dev, info->gpio_nce,
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GPIOF_OUT_INIT_HIGH, "NAND nCE");
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if (ret)
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return ret;
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ret = devm_gpio_request_one(info->dev, info->gpio_nrw,
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GPIOF_OUT_INIT_HIGH, "NAND nRW");
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if (ret)
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return ret;
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ret = devm_gpio_request_one(info->dev, info->gpio_cle,
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GPIOF_OUT_INIT_LOW, "NAND CLE");
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if (ret)
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return ret;
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ret = devm_gpio_request_one(info->dev, info->gpio_ale,
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GPIOF_OUT_INIT_LOW, "NAND ALE");
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if (ret)
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return ret;
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ret = devm_gpio_request_one(info->dev, info->gpio_read,
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GPIOF_OUT_INIT_LOW, "NAND READ");
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if (ret)
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return ret;
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ret = devm_gpio_request_one(info->dev, info->gpio_rdy,
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GPIOF_IN, "NAND RDY");
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return ret;
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}
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static int rb91x_nand_probe(struct platform_device *pdev)
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{
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struct rb91x_nand_info *rbni;
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struct rb91x_nand_platform_data *pdata;
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struct mtd_info *mtd;
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int ret;
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pr_info(DRV_DESC "\n");
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata)
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return -EINVAL;
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rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL);
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if (!rbni)
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return -ENOMEM;
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rbni->dev = &pdev->dev;
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rbni->gpio_nce = pdata->gpio_nce;
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rbni->gpio_ale = pdata->gpio_ale;
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rbni->gpio_cle = pdata->gpio_cle;
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rbni->gpio_read = pdata->gpio_read;
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rbni->gpio_nrw = pdata->gpio_nrw;
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rbni->gpio_rdy = pdata->gpio_rdy;
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rbni->gpio_nle = pdata->gpio_nle;
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rbni->chip.priv = &rbni;
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mtd = rbinfo_to_mtd(rbni);
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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mtd->priv = &rbni->chip;
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#endif
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mtd->owner = THIS_MODULE;
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rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl;
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rbni->chip.dev_ready = rb91x_nand_dev_ready;
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rbni->chip.read_byte = rb91x_nand_read_byte;
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rbni->chip.write_buf = rb91x_nand_write_buf;
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rbni->chip.read_buf = rb91x_nand_read_buf;
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rbni->chip.chip_delay = 25;
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rbni->chip.ecc.mode = NAND_ECC_SOFT;
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
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rbni->chip.ecc.algo = NAND_ECC_HAMMING;
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#endif
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rbni->chip.options = NAND_NO_SUBPAGE_WRITE;
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platform_set_drvdata(pdev, rbni);
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ret = rb91x_nand_gpio_init(rbni);
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if (ret)
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return ret;
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ret = nand_scan_ident(mtd, 1, NULL);
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if (ret)
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return ret;
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if (mtd->writesize == 512)
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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rbni->chip.ecc.layout = &rb91x_nand_ecclayout;
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#else
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mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
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#endif
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ret = nand_scan_tail(mtd);
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if (ret)
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return ret;
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ret = mtd_device_register(mtd, rb91x_nand_partitions,
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ARRAY_SIZE(rb91x_nand_partitions));
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if (ret)
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goto err_release_nand;
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return 0;
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err_release_nand:
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nand_release(mtd);
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return ret;
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}
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static int rb91x_nand_remove(struct platform_device *pdev)
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{
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struct rb91x_nand_info *info = platform_get_drvdata(pdev);
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nand_release(rbinfo_to_mtd(info));
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return 0;
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}
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static struct platform_driver rb91x_nand_driver = {
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.probe = rb91x_nand_probe,
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.remove = rb91x_nand_remove,
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.driver = {
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.name = RB91X_NAND_DRIVER_NAME,
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(rb91x_nand_driver);
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MODULE_DESCRIPTION(DRV_DESC);
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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MODULE_LICENSE("GPL v2");
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