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43 lines
1.2 KiB
Diff
43 lines
1.2 KiB
Diff
From a7ef1eaddbf4bd50bfee92d9dfbecadc61467bbf Mon Sep 17 00:00:00 2001
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From: Kevin Cernekee <cernekee@gmail.com>
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Date: Mon, 20 Oct 2014 21:27:57 -0700
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Subject: [PATCH] MIPS: Allow MIPS_CPU_SCACHE to be used with different line
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sizes
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CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However,
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it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the
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L1_SHIFT selection into the CPU or SoC section so that other SoCs can
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select different values.
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
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Cc: f.fainelli@gmail.com
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Cc: mbizon@freebox.fr
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Cc: jogo@openwrt.org
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Cc: jfraser@broadcom.com
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Cc: linux-mips@linux-mips.org
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Cc: devicetree@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/8162/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/Kconfig | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -315,6 +315,7 @@ config MIPS_MALTA
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select I8259
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select MIPS_BONITO64
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select MIPS_CPU_SCACHE
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+ select MIPS_L1_CACHE_SHIFT_6
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select PCI_GT64XXX_PCI0
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select MIPS_MSC
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select SWAP_IO_SPACE
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@@ -1820,7 +1821,6 @@ config IP22_CPU_SCACHE
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config MIPS_CPU_SCACHE
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bool
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select BOARD_SCACHE
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- select MIPS_L1_CACHE_SHIFT_6
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config R5000_CPU_SCACHE
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bool
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