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232 lines
7.7 KiB
C
232 lines
7.7 KiB
C
#ifndef IFXMIPS_ATM_PPE_COMMON_H
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#define IFXMIPS_ATM_PPE_COMMON_H
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#if defined(CONFIG_LANTIQ)
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#include "ifxmips_atm_ppe_danube.h"
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#define CONFIG_DANUBE
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#elif defined(CONFIG_DANUBE)
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#include "ifxmips_atm_ppe_danube.h"
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#elif defined(CONFIG_AMAZON_SE)
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#include "ifxmips_atm_ppe_amazon_se.h"
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#elif defined(CONFIG_AR9)
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#include "ifxmips_atm_ppe_ar9.h"
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#elif defined(CONFIG_VR9)
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#include "ifxmips_atm_ppe_vr9.h"
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#else
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#error Platform is not specified!
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#endif
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/*
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* Code/Data Memory (CDM) Interface Configuration Register
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*/
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#define CDM_CFG PPE_REG_ADDR(0x0100)
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#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2)
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#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1))
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#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value)
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#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0)
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/*
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* QSB Internal Cell Delay Variation Register
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*/
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#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007)
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#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0)
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#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value)
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/*
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* QSB Scheduler Burst Limit Register
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*/
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#define QSB_SBL QSB_CONF_REG_ADDR(0x0009)
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#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0)
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#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value)
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/*
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* QSB Configuration Register
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*/
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#define QSB_CFG QSB_CONF_REG_ADDR(0x000A)
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#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0)
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#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value)
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/*
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* QSB RAM Transfer Table Register
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*/
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#define QSB_RTM QSB_CONF_REG_ADDR(0x000B)
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#define QSB_RTM_DM (*QSB_RTM)
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#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF)
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/*
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* QSB RAM Transfer Data Register
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*/
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#define QSB_RTD QSB_CONF_REG_ADDR(0x000C)
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#define QSB_RTD_TTV (*QSB_RTD)
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#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF)
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/*
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* QSB RAM Access Register
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*/
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#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D)
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#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31))
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#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24)
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#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16))
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#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0)
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#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0)
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#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value)
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#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0)
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#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value)
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/*
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* QSB Queue Scheduling and Shaping Definitions
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*/
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#define QSB_WFQ_NONUBR_MAX 0x3f00
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#define QSB_WFQ_UBR_BYPASS 0x3fff
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#define QSB_TP_TS_MAX 65472
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#define QSB_TAUS_MAX 64512
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#define QSB_GCR_MIN 18
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/*
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* QSB Constant
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*/
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#define QSB_RAMAC_RW_READ 0
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#define QSB_RAMAC_RW_WRITE 1
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#define QSB_RAMAC_TSEL_QPT 0x01
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#define QSB_RAMAC_TSEL_SCT 0x02
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#define QSB_RAMAC_TSEL_SPT 0x03
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#define QSB_RAMAC_TSEL_VBR 0x08
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#define QSB_RAMAC_LH_LOW 0
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#define QSB_RAMAC_LH_HIGH 1
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#define QSB_QPT_SET_MASK 0x0
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#define QSB_QVPT_SET_MASK 0x0
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#define QSB_SET_SCT_MASK 0x0
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#define QSB_SET_SPT_MASK 0x0
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#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF
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#define QSB_SPT_SBV_VALID (1 << 31)
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#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0)
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#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value)
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/*
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* QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry
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*/
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#if defined(__BIG_ENDIAN)
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union qsb_queue_parameter_table {
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struct {
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unsigned int res1 :1;
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unsigned int vbr :1;
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unsigned int wfqf :14;
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unsigned int tp :16;
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} bit;
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u32 dword;
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};
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union qsb_queue_vbr_parameter_table {
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struct {
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unsigned int taus :16;
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unsigned int ts :16;
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} bit;
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u32 dword;
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};
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#else
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union qsb_queue_parameter_table {
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struct {
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unsigned int tp :16;
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unsigned int wfqf :14;
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unsigned int vbr :1;
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unsigned int res1 :1;
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} bit;
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u32 dword;
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};
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union qsb_queue_vbr_parameter_table {
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struct {
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unsigned int ts :16;
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unsigned int taus :16;
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} bit;
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u32 dword;
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};
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#endif // defined(__BIG_ENDIAN)
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/*
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* Mailbox IGU0 Registers
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*/
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#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200)
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#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201)
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#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202)
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#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203)
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#define MBOX_IGU0_ISRS_SET(n) (1 << (n))
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#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n))
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#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n)))
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#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n)))
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#define MBOX_IGU0_IER_EN_SET(n) (1 << (n))
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/*
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* Mailbox IGU1 Registers
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*/
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#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204)
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#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205)
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#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206)
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#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207)
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#define MBOX_IGU1_ISRS_SET(n) (1 << (n))
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#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n))
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#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n)))
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#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n)))
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#define MBOX_IGU1_IER_EN_SET(n) (1 << (n))
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/*
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* Mailbox IGU3 Registers
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*/
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#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214)
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#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215)
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#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216)
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#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217)
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#define MBOX_IGU3_ISRS_SET(n) (1 << (n))
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#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n))
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#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n)))
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#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n)))
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#define MBOX_IGU3_IER_EN_SET(n) (1 << (n))
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/*
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* RTHA/TTHA Registers
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*/
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#define SFSM_STATE0 PPE_REG_ADDR(0x0410)
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#define SFSM_STATE1 PPE_REG_ADDR(0x0411)
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#define SFSM_DBA0 PPE_REG_ADDR(0x0412)
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#define SFSM_DBA1 PPE_REG_ADDR(0x0413)
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#define SFSM_CBA0 PPE_REG_ADDR(0x0414)
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#define SFSM_CBA1 PPE_REG_ADDR(0x0415)
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#define SFSM_CFG0 PPE_REG_ADDR(0x0416)
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#define SFSM_CFG1 PPE_REG_ADDR(0x0417)
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#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C)
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#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D)
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#define FFSM_DBA0 PPE_REG_ADDR(0x0508)
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#define FFSM_DBA1 PPE_REG_ADDR(0x0509)
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#define FFSM_CFG0 PPE_REG_ADDR(0x050A)
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#define FFSM_CFG1 PPE_REG_ADDR(0x050B)
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#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E)
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#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F)
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#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514)
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#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515)
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#endif // IFXMIPS_ATM_PPE_COMMON_H
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