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49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
From 97a21ddbd77a52a444560be76dfd9e0a58ddb141 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Mon, 25 Jan 2016 13:52:41 -0800
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Subject: [PATCH] drm/vc4: Fix the clear color for the first tile rendered.
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Apparently in hardware (as opposed to simulation), the clear colors
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need to be uploaded before the render config, otherwise they won't
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take effect. Fixes igt's vc4_wait_bo/used-bo-* subtests.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/gpu/drm/vc4/vc4_render_cl.c | 18 +++++++++---------
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1 file changed, 9 insertions(+), 9 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
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+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
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@@ -321,15 +321,6 @@ static int vc4_create_rcl_bo(struct drm_
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list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head,
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&exec->unref_list);
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- rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
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- rcl_u32(setup,
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- (setup->color_write ? (setup->color_write->paddr +
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- args->color_write.offset) :
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- 0));
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- rcl_u16(setup, args->width);
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- rcl_u16(setup, args->height);
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- rcl_u16(setup, args->color_write.bits);
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-
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/* The tile buffer gets cleared when the previous tile is stored. If
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* the clear values changed between frames, then the tile buffer has
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* stale clear values in it, so we have to do a store in None mode (no
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@@ -349,6 +340,15 @@ static int vc4_create_rcl_bo(struct drm_
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rcl_u32(setup, 0); /* no address, since we're in None mode */
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}
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+ rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
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+ rcl_u32(setup,
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+ (setup->color_write ? (setup->color_write->paddr +
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+ args->color_write.offset) :
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+ 0));
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+ rcl_u16(setup, args->width);
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+ rcl_u16(setup, args->height);
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+ rcl_u16(setup, args->color_write.bits);
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+
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for (y = min_y_tile; y <= max_y_tile; y++) {
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for (x = min_x_tile; x <= max_x_tile; x++) {
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bool first = (x == min_x_tile && y == min_y_tile);
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