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118 lines
3.8 KiB
Diff
118 lines
3.8 KiB
Diff
From 8a0bf079f870379a1e392819ac1116d74500ec01 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
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Date: Fri, 4 Oct 2019 15:07:41 +0300
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Subject: [PATCH] MLKU-114-3 crypto: caam - OP-TEE firmware support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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caam driver needs to be aware of OP-TEE f/w presence, since some things
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are done differently:
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1. there is no access to controller's register page (note however that
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some registers are aliased in job rings' register pages)
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It's worth mentioning that due to this, MCFGR[PS] cannot be read
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and driver assumes MCFGR[PS] = b'0 - engine using 32-bit address pointers.
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This is in sync with the fact that:
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-all i.MX SoCs currently use MCFGR[PS] = b'0
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-only i.MX OP-TEE use cases don't allow access to controller register page
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Note: When DN OP-TEE will start enforcing the same policy,
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this solution will stop working and information about caam configuration
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will have to deduced in some other way.
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2. as a consequence of "1.", part of the initialization is moved in
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other f/w (TF-A etc.), e.g. RNG initialization
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Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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---
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drivers/crypto/caam/ctrl.c | 22 ++++++++++++++++++----
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drivers/crypto/caam/intern.h | 1 +
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2 files changed, 19 insertions(+), 4 deletions(-)
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--- a/drivers/crypto/caam/ctrl.c
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+++ b/drivers/crypto/caam/ctrl.c
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@@ -583,6 +583,7 @@ static int caam_probe(struct platform_de
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u8 rng_vid;
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int pg_size;
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int BLOCK_OFFSET = 0;
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+ bool reg_access = true;
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ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
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if (!ctrlpriv)
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@@ -600,6 +601,8 @@ static int caam_probe(struct platform_de
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ctrlpriv->scu_en = !!np;
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of_node_put(np);
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+ reg_access = !ctrlpriv->scu_en;
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+
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/*
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* CAAM clocks cannot be controlled from kernel.
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* They are automatically turned on by SCU f/w.
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@@ -607,6 +610,17 @@ static int caam_probe(struct platform_de
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if (ctrlpriv->scu_en)
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goto iomap_ctrl;
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+ /*
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+ * Until Layerscape and i.MX OP-TEE get in sync,
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+ * only i.MX OP-TEE use cases disallow access to
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+ * caam page 0 (controller) registers.
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+ */
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+ np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
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+ ctrlpriv->optee_en = !!np;
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+ of_node_put(np);
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+
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+ reg_access = reg_access && !ctrlpriv->optee_en;
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+
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if (!imx_soc_match->data) {
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dev_err(dev, "No clock data provided for i.MX SoC");
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return -EINVAL;
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@@ -657,7 +671,7 @@ iomap_ctrl:
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caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
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(CSTA_PLEND | CSTA_ALT_PLEND));
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comp_params = rd_reg32(&perfmon->comp_parms_ms);
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- if (!ctrlpriv->scu_en && comp_params & CTPR_MS_PS &&
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+ if (reg_access && comp_params & CTPR_MS_PS &&
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rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
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caam_ptr_sz = sizeof(u64);
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else
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@@ -708,7 +722,7 @@ iomap_ctrl:
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/* Get the IRQ of the controller (for security violations only) */
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ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
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- if (ctrlpriv->scu_en)
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+ if (!reg_access)
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goto set_dma_mask;
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/*
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@@ -801,7 +815,7 @@ set_dma_mask:
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return -ENOMEM;
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}
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- if (ctrlpriv->scu_en)
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+ if (!reg_access)
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goto report_live;
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if (ctrlpriv->era < 10) {
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@@ -928,7 +942,7 @@ report_live:
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ctrlpriv->ctl, &perfmon->status,
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&caam_fops_u32_ro);
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- if (ctrlpriv->scu_en)
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+ if (!reg_access)
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goto probe_jrs;
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/* Internal covering keys (useful in non-secure mode only) */
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--- a/drivers/crypto/caam/intern.h
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+++ b/drivers/crypto/caam/intern.h
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@@ -83,6 +83,7 @@ struct caam_drv_private {
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u8 qi_present; /* Nonzero if QI present in device */
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u8 mc_en; /* Nonzero if MC f/w is active */
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u8 scu_en; /* Nonzero if SCU f/w is active */
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++ u8 optee_en; /* Nonzero if OP-TEE f/w is active */
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int secvio_irq; /* Security violation interrupt number */
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int virt_en; /* Virtualization enabled in CAAM */
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int era; /* CAAM Era (internal HW revision) */
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