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207 lines
6.0 KiB
Diff
207 lines
6.0 KiB
Diff
From 46a704b1b093f4053eceaf8e5f0ab54949afa532 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 19 Jan 2013 08:54:24 +0000
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Subject: [PATCH 17/40] MIPS: lantiq: adds static clock for PP32
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The Lantiq DSL SoCs have an internal networking processor. Add code to read
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the static clock rate.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4815/
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---
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arch/mips/include/asm/mach-lantiq/lantiq.h | 1 +
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arch/mips/lantiq/clk.c | 12 ++++++--
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arch/mips/lantiq/clk.h | 7 ++++-
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arch/mips/lantiq/falcon/sysctrl.c | 4 +--
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arch/mips/lantiq/xway/clk.c | 43 ++++++++++++++++++++++++++++
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arch/mips/lantiq/xway/sysctrl.c | 12 ++++----
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6 files changed, 69 insertions(+), 10 deletions(-)
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--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
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@@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *c
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extern struct clk *clk_get_cpu(void);
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extern struct clk *clk_get_fpi(void);
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extern struct clk *clk_get_io(void);
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+extern struct clk *clk_get_ppe(void);
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/* find out what bootsource we have */
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extern unsigned char ltq_boot_select(void);
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--- a/arch/mips/lantiq/clk.c
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+++ b/arch/mips/lantiq/clk.c
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@@ -26,13 +26,15 @@
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#include "prom.h"
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/* lantiq socs have 3 static clocks */
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-static struct clk cpu_clk_generic[3];
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+static struct clk cpu_clk_generic[4];
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-void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
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+void clkdev_add_static(unsigned long cpu, unsigned long fpi,
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+ unsigned long io, unsigned long ppe)
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{
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cpu_clk_generic[0].rate = cpu;
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cpu_clk_generic[1].rate = fpi;
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cpu_clk_generic[2].rate = io;
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+ cpu_clk_generic[3].rate = ppe;
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}
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struct clk *clk_get_cpu(void)
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@@ -51,6 +53,12 @@ struct clk *clk_get_io(void)
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return &cpu_clk_generic[2];
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}
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+struct clk *clk_get_ppe(void)
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+{
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+ return &cpu_clk_generic[3];
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+}
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+EXPORT_SYMBOL_GPL(clk_get_ppe);
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+
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static inline int clk_good(struct clk *clk)
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{
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return clk && !IS_ERR(clk);
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--- a/arch/mips/lantiq/clk.h
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+++ b/arch/mips/lantiq/clk.h
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@@ -27,12 +27,15 @@
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#define CLOCK_167M 166666667
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#define CLOCK_196_608M 196608000
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#define CLOCK_200M 200000000
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+#define CLOCK_222M 222000000
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+#define CLOCK_240M 240000000
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#define CLOCK_250M 250000000
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#define CLOCK_266M 266666666
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#define CLOCK_300M 300000000
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#define CLOCK_333M 333333333
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#define CLOCK_393M 393215332
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#define CLOCK_400M 400000000
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+#define CLOCK_450M 450000000
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#define CLOCK_500M 500000000
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#define CLOCK_600M 600000000
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@@ -64,15 +67,17 @@ struct clk {
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};
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extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
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- unsigned long io);
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+ unsigned long io, unsigned long ppe);
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extern unsigned long ltq_danube_cpu_hz(void);
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extern unsigned long ltq_danube_fpi_hz(void);
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+extern unsigned long ltq_danube_pp32_hz(void);
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extern unsigned long ltq_ar9_cpu_hz(void);
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extern unsigned long ltq_ar9_fpi_hz(void);
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extern unsigned long ltq_vr9_cpu_hz(void);
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extern unsigned long ltq_vr9_fpi_hz(void);
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+extern unsigned long ltq_vr9_pp32_hz(void);
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#endif
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--- a/arch/mips/lantiq/falcon/sysctrl.c
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+++ b/arch/mips/lantiq/falcon/sysctrl.c
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@@ -241,9 +241,9 @@ void __init ltq_soc_init(void)
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/* get our 3 static rates for cpu, fpi and io clocks */
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if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
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- clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
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+ clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
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else
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- clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
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+ clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
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/* add our clock domains */
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clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
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--- a/arch/mips/lantiq/xway/clk.c
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+++ b/arch/mips/lantiq/xway/clk.c
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@@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
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}
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}
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+unsigned long ltq_danube_pp32_hz(void)
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+{
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+ unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
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+ unsigned long clk;
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+
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+ switch (clksys) {
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+ case 1:
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+ clk = CLOCK_240M;
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+ break;
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+ case 2:
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+ clk = CLOCK_222M;
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+ break;
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+ case 3:
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+ clk = CLOCK_133M;
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+ break;
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+ default:
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+ clk = CLOCK_266M;
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+ break;
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+ }
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+
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+ return clk;
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+}
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+
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unsigned long ltq_ar9_sys_hz(void)
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{
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if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
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@@ -147,5 +170,25 @@ unsigned long ltq_vr9_fpi_hz(void)
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break;
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}
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+ return clk;
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+}
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+
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+unsigned long ltq_vr9_pp32_hz(void)
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+{
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+ unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
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+ unsigned long clk;
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+
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+ switch (clksys) {
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+ case 1:
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+ clk = CLOCK_450M;
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+ break;
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+ case 2:
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+ clk = CLOCK_300M;
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+ break;
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+ default:
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+ clk = CLOCK_500M;
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+ break;
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+ }
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+
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return clk;
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}
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
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if (of_machine_is_compatible("lantiq,ase")) {
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if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
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- clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
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+ clkdev_add_static(CLOCK_266M, CLOCK_133M,
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+ CLOCK_133M, CLOCK_266M);
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else
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- clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
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+ clkdev_add_static(CLOCK_133M, CLOCK_133M,
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+ CLOCK_133M, CLOCK_133M);
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clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
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clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
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} else if (of_machine_is_compatible("lantiq,vr9")) {
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clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
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- ltq_vr9_fpi_hz());
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+ ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
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clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
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clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
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clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
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@@ -376,10 +378,10 @@ void __init ltq_soc_init(void)
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PMU_PPE_QSB | PMU_PPE_TOP);
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} else if (of_machine_is_compatible("lantiq,ar9")) {
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clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
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- ltq_ar9_fpi_hz());
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+ ltq_ar9_fpi_hz(), CLOCK_250M);
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clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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- ltq_danube_fpi_hz());
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+ ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
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}
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}
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