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64 lines
2.7 KiB
Diff
64 lines
2.7 KiB
Diff
From 502af2ba683831fb4c05bd887374053d17376c87 Mon Sep 17 00:00:00 2001
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From: P33M <p33m@github.com>
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Date: Fri, 21 Sep 2018 14:05:09 +0100
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Subject: [PATCH 420/454] dwc_otg: fiq_fsm: fix incorrect DMA register offset
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calculation
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Rationalise the offset and update all call sites.
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Fixes https://github.com/raspberrypi/linux/issues/2408
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---
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drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 8 ++++----
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drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 2 +-
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2 files changed, 5 insertions(+), 5 deletions(-)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
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@@ -250,7 +250,7 @@ static int notrace fiq_increment_dma_buf
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BUG();
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hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
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- FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
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+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
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st->channel[n].dma_info.index = i;
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return 0;
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}
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@@ -302,7 +302,7 @@ static int notrace fiq_iso_out_advance(s
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/* New DMA address - address of bounce buffer referred to in index */
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hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
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- //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
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+ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);
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//hcdma.d32 += st->channel[n].dma_info.slot_len[i];
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fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
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fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
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@@ -317,7 +317,7 @@ static int notrace fiq_iso_out_advance(s
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st->channel[n].dma_info.index++;
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FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
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FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
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- FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
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+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
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return last;
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}
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@@ -564,7 +564,7 @@ static int notrace noinline fiq_fsm_upda
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/* grab the next DMA address offset from the array */
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hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
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- FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
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+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);
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/* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
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* the core needs to be told to send the correct number. Caution: for IN transfers,
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--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
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@@ -94,7 +94,7 @@ do { \
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#define HC_START 0x500
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#define HC_OFFSET 0x020
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-#define HC_DMA 0x514
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+#define HC_DMA 0x14
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#define HCCHAR 0x00
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#define HCSPLT 0x04
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