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203 lines
7.1 KiB
Diff
203 lines
7.1 KiB
Diff
From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Fri, 6 Jan 2017 17:40:12 +0100
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Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
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This adds code to initialize the USB controller and PHY also on Danube,
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Amazon SE and AR10. This code is based on the Vendor driver from
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different UGW versions and compared to the hardware documentation.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/mips/lantiq/xway/reset.c | 120 ++++++++++++++++++++++++++++++----------
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arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
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2 files changed, 110 insertions(+), 30 deletions(-)
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--- a/arch/mips/lantiq/xway/reset.c
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+++ b/arch/mips/lantiq/xway/reset.c
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@@ -72,6 +72,8 @@
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#define RCU_USBCFG_HDSEL_BIT BIT(11)
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#define RCU_USBCFG_HOST_END_BIT BIT(10)
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#define RCU_USBCFG_SLV_END_BIT BIT(9)
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+#define RCU_USBCFG_SLV_END_BIT_AR9 BIT(17)
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+
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/* USB reset bits */
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#define RCU_USBRESET 0x0010
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@@ -85,6 +87,8 @@
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#define RCU_CFG1A 0x0038
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#define RCU_CFG1B 0x003C
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+#define RCU_CFG1_TX_PEE BIT(0)
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+#define RCU_CFG1_DIS_THR_SHIFT 15 /* Disconnect Threshold */
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/* USB PMU devices */
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#define PMU_AHBM BIT(15)
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@@ -306,38 +310,91 @@ static void ltq_usb_init(void)
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/* Power for USB cores 1 & 2 */
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ltq_pmu_enable(PMU_AHBM);
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ltq_pmu_enable(PMU_USB0);
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- ltq_pmu_enable(PMU_USB1);
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- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
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- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
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+ if (of_machine_is_compatible("lantiq,ar10") ||
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+ of_machine_is_compatible("lantiq,grx390") ||
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+ of_machine_is_compatible("lantiq,ar9") ||
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+ of_machine_is_compatible("lantiq,vr9"))
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+ ltq_pmu_enable(PMU_USB1);
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+
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+ if (of_machine_is_compatible("lantiq,vr9") ||
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+ of_machine_is_compatible("lantiq,ar10")) {
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | RCU_CFG1_TX_PEE |
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+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1A);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | RCU_CFG1_TX_PEE |
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+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1B);
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+ }
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/* Enable USB PHY power for cores 1 & 2 */
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ltq_pmu_enable(PMU_USB0_P);
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- ltq_pmu_enable(PMU_USB1_P);
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+ if (of_machine_is_compatible("lantiq,ar10") ||
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+ of_machine_is_compatible("lantiq,grx390") ||
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+ of_machine_is_compatible("lantiq,ar9") ||
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+ of_machine_is_compatible("lantiq,vr9"))
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+ ltq_pmu_enable(PMU_USB1_P);
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+
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+ if (of_machine_is_compatible("lantiq,ase") ||
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+ of_machine_is_compatible("lantiq,danube")) {
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+ /* Configure cores to host mode */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
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+ RCU_USB1CFG);
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+
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+ /* Select DMA endianness (Host-endian: big-endian) */
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+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
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+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
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+ }
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+
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+ if (of_machine_is_compatible("lantiq,ar9")) {
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+ /* Configure cores to host mode */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
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+ RCU_USB1CFG);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
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+ RCU_USB2CFG);
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+
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+ /* Select DMA endianness (Host-endian: big-endian) */
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+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
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+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
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+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
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+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
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+ }
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+
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+ if (of_machine_is_compatible("lantiq,vr9") ||
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+ of_machine_is_compatible("lantiq,ar10")) {
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+ /* Configure cores to host mode */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
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+ RCU_USB1CFG);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
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+ RCU_USB2CFG);
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+
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+ /* Select DMA endianness (Host-endian: big-endian) */
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+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
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+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
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+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
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+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
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+ }
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+
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+ if (of_machine_is_compatible("lantiq,ar9")) {
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+ /* Hard reset USB state machines */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
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+ | USBRESET_BIT | BIT(28), RCU_USBRESET);
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+ udelay(50 * 1000);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
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+ & ~(USBRESET_BIT | BIT(28)), RCU_USBRESET);
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+ } else {
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+ /* Hard reset USB state machines */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
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+ udelay(50 * 1000);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
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+ }
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- /* Configure cores to host mode */
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- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
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- RCU_USB1CFG);
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- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
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- RCU_USB2CFG);
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-
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- /* Select DMA endianness (Host-endian: big-endian) */
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- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
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- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
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- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
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- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
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-
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- /* Hard reset USB state machines */
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- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
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- udelay(50 * 1000);
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- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
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-
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- /* Soft reset USB state machines */
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- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
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- udelay(50 * 1000);
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- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
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+ if (of_machine_is_compatible("lantiq,vr9")) {
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+ /* Soft reset USB state machines */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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+ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
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+ udelay(50 * 1000);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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+ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
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+ }
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}
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static int __init mips_reboot_setup(void)
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@@ -363,8 +420,11 @@ static int __init mips_reboot_setup(void
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if (!ltq_rcu_membase)
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panic("Failed to remap core memory");
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- if (of_machine_is_compatible("lantiq,ar9") ||
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- of_machine_is_compatible("lantiq,vr9"))
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+ if (of_machine_is_compatible("lantiq,danube") ||
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+ of_machine_is_compatible("lantiq,ase") ||
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+ of_machine_is_compatible("lantiq,ar9") ||
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+ of_machine_is_compatible("lantiq,vr9") ||
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+ of_machine_is_compatible("lantiq,ar10"))
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ltq_usb_init();
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if (of_machine_is_compatible("lantiq,vr9"))
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -254,6 +254,25 @@ static void pmu_disable(struct clk *clk)
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pr_warn("deactivating PMU module failed!");
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}
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+static void usb_set_clock(void)
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+{
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+ unsigned int val = ltq_cgu_r32(ifccr);
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+
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+ if (of_machine_is_compatible("lantiq,ar10") ||
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+ of_machine_is_compatible("lantiq,grx390")) {
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+ val &= ~0x03; /* XTAL divided by 3 */
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+ } else if (of_machine_is_compatible("lantiq,ar9") ||
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+ of_machine_is_compatible("lantiq,vr9")) {
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+ /* TODO: this depends on the XTAL frequency */
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+ val |= 0x03; /* XTAL divided by 3 */
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+ } else if (of_machine_is_compatible("lantiq,ase")) {
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+ val |= 0x20; /* from XTAL */
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+ } else if (of_machine_is_compatible("lantiq,danube")) {
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+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
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+ }
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+ ltq_cgu_w32(val, ifccr);
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+}
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+
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/* the pci enable helper */
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static int pci_enable(struct clk *clk)
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{
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@@ -608,4 +627,5 @@ void __init ltq_soc_init(void)
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if (of_machine_is_compatible("lantiq,vr9"))
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xbar_fpi_burst_disable();
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+ usb_set_clock();
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}
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