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194 lines
4.9 KiB
C
194 lines
4.9 KiB
C
/*
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* OpenMesh OM5P-AC support
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*
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* Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
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* Copyright (C) 2014 Sven Eckelmann <sven@open-mesh.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/i2c-gpio.h>
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#include <linux/platform_data/phy-at803x.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#include "pci.h"
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#define OM5PAC_GPIO_LED_POWER 18
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#define OM5PAC_GPIO_LED_GREEN 21
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#define OM5PAC_GPIO_LED_RED 23
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#define OM5PAC_GPIO_LED_YELLOW 22
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#define OM5PAC_GPIO_LED_LAN 20
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#define OM5PAC_GPIO_LED_WAN 19
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#define OM5PAC_GPIO_I2C_SCL 12
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#define OM5PAC_GPIO_I2C_SDA 11
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#define OM5PAC_KEYS_POLL_INTERVAL 20 /* msecs */
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#define OM5PAC_KEYS_DEBOUNCE_INTERVAL (3 * OM5PAC_KEYS_POLL_INTERVAL)
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#define OM5PAC_WMAC_CALDATA_OFFSET 0x1000
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static struct gpio_led om5pac_leds_gpio[] __initdata = {
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{
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.name = "om5pac:blue:power",
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.gpio = OM5PAC_GPIO_LED_POWER,
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.active_low = 1,
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}, {
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.name = "om5pac:red:wifi",
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.gpio = OM5PAC_GPIO_LED_RED,
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.active_low = 1,
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}, {
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.name = "om5pac:yellow:wifi",
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.gpio = OM5PAC_GPIO_LED_YELLOW,
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.active_low = 1,
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}, {
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.name = "om5pac:green:wifi",
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.gpio = OM5PAC_GPIO_LED_GREEN,
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.active_low = 1,
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}, {
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.name = "om5pac:blue:lan",
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.gpio = OM5PAC_GPIO_LED_LAN,
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.active_low = 1,
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}, {
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.name = "om5pac:blue:wan",
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.gpio = OM5PAC_GPIO_LED_WAN,
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.active_low = 1,
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}
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};
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static struct flash_platform_data om5pac_flash_data = {
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.type = "mx25l12805d",
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};
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static struct i2c_gpio_platform_data om5pac_i2c_device_platdata = {
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.sda_pin = OM5PAC_GPIO_I2C_SDA,
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.scl_pin = OM5PAC_GPIO_I2C_SCL,
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.udelay = 10,
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.sda_is_open_drain = 1,
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.scl_is_open_drain = 1,
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};
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static struct platform_device om5pac_i2c_device = {
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.name = "i2c-gpio",
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.id = 0,
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.dev = {
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.platform_data = &om5pac_i2c_device_platdata,
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},
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};
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static struct i2c_board_info om5pac_i2c_devs[] __initdata = {
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{
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I2C_BOARD_INFO("tmp423", 0x4c),
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},
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};
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static struct at803x_platform_data om5pac_at803x_data = {
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.disable_smarteee = 1,
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.enable_rgmii_rx_delay = 1,
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.enable_rgmii_tx_delay = 1,
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};
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static struct mdio_board_info om5pac_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 1,
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.platform_data = &om5pac_at803x_data,
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},
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 2,
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.platform_data = &om5pac_at803x_data,
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},
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};
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static void __init om5p_ac_setup_qca955x_eth_cfg(u32 mask,
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unsigned int rxd,
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unsigned int rxdv,
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unsigned int txd,
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unsigned int txe)
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{
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void __iomem *base;
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u32 t;
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base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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t = mask;
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t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
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t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
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t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
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t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
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__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
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iounmap(base);
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}
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static void __init om5p_ac_setup(void)
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{
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u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
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u8 mac[6];
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/* temperature sensor */
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platform_device_register(&om5pac_i2c_device);
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i2c_register_board_info(0, om5pac_i2c_devs,
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ARRAY_SIZE(om5pac_i2c_devs));
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ath79_gpio_output_select(OM5PAC_GPIO_LED_WAN, QCA955X_GPIO_OUT_GPIO);
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ath79_register_m25p80(&om5pac_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pac_leds_gpio),
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om5pac_leds_gpio);
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ath79_init_mac(mac, art, 0x02);
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ath79_register_wmac(art + OM5PAC_WMAC_CALDATA_OFFSET, mac);
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om5p_ac_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
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ath79_register_mdio(0, 0x0);
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mdiobus_register_board_info(om5pac_mdio0_info,
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ARRAY_SIZE(om5pac_mdio0_info));
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ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
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ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
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/* GMAC0 is connected to the PHY1 */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_data.phy_mask = BIT(1);
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ath79_eth0_pll_data.pll_1000 = 0x82000101;
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ath79_eth0_pll_data.pll_100 = 0x80000101;
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ath79_eth0_pll_data.pll_10 = 0x80001313;
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ath79_register_eth(0);
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/* GMAC1 is connected to MDIO1 in SGMII mode */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
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ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth1_data.phy_mask = BIT(2);
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ath79_eth1_pll_data.pll_1000 = 0x03000101;
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ath79_eth1_pll_data.pll_100 = 0x80000101;
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ath79_eth1_pll_data.pll_10 = 0x80001313;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_register_eth(1);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_OM5P_AC, "OM5P-AC", "OpenMesh OM5P AC", om5p_ac_setup);
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