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105 lines
3.4 KiB
Diff
105 lines
3.4 KiB
Diff
From 6031a240816d1c9a10f596d0648e586f6b878809 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Tue, 15 Mar 2011 12:33:41 +0100
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Subject: [PATCH 3/7] NAND: Add support for subpage reads for
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NAND_ECC_HW_OOB_FIRST
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---
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drivers/mtd/nand/nand_base.c | 77 +++++++++++++++++++++++++++++++++++++++++-
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1 file changed, 76 insertions(+), 1 deletion(-)
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--- a/drivers/mtd/nand/nand_base.c
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+++ b/drivers/mtd/nand/nand_base.c
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@@ -1398,6 +1398,75 @@ static int nand_read_page_hwecc_oob_firs
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}
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/**
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+ * nand_read_subpage_hwecc_oob_first - [REPLACABLE] hw ecc based sub-page read function
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+ * @mtd: mtd info structure
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+ * @chip: nand chip info structure
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+ * @data_offs: offset of requested data within the page
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+ * @readlen: data length
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+ * @bufpoi: buffer to store read data
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+ * @page: page number to read
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+ *
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+ * Hardware ECC for large page chips, require OOB to be read first.
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+ * For this ECC mode, the write_page method is re-used from ECC_HW.
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+ * These methods read/write ECC from the OOB area, unlike the
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+ * ECC_HW_SYNDROME support with multiple ECC steps, follows the
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+ * "infix ECC" scheme and reads/writes ECC from the data area, by
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+ * overwriting the NAND manufacturer bad block markings.
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+ */
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+static int nand_read_subpage_hwecc_oob_first(struct mtd_info *mtd, struct nand_chip *chip,
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+ uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, int page)
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+{
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+ int start_step, end_step, num_steps;
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+ uint32_t *eccpos = chip->ecc.layout->eccpos;
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+ uint8_t *p;
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+ int data_col_addr;
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+ int eccsize = chip->ecc.size;
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+ int eccbytes = chip->ecc.bytes;
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+ uint8_t *ecc_code = chip->buffers->ecccode;
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+ uint8_t *ecc_calc = chip->buffers->ecccalc;
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+ int i;
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+
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+ /* Column address wihin the page aligned to ECC size */
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+ start_step = data_offs / chip->ecc.size;
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+ end_step = (data_offs + readlen - 1) / chip->ecc.size;
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+ num_steps = end_step - start_step + 1;
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+
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+ data_col_addr = start_step * chip->ecc.size;
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+
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+ /* Read the OOB area first */
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+ if (mtd->writesize > 512) {
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+ chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
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+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
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+ } else {
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+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
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+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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+ chip->cmdfunc(mtd, NAND_CMD_READ0, data_col_addr, page);
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+ }
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+
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+ for (i = 0; i < chip->ecc.total; i++)
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+ ecc_code[i] = chip->oob_poi[eccpos[i]];
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+
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+ p = bufpoi + data_col_addr;
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+
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+ for (i = eccbytes * start_step; num_steps; num_steps--, i += eccbytes, p += eccsize) {
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+ int stat;
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+
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+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
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+ chip->read_buf(mtd, p, eccsize);
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+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
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+
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+ stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
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+ if (stat < 0)
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+ mtd->ecc_stats.failed++;
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+ else
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+ mtd->ecc_stats.corrected += stat;
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+ }
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+
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+ return 0;
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+}
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+
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+/**
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* nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
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* @mtd: mtd info structure
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* @chip: nand chip info structure
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@@ -3961,8 +4030,14 @@ int nand_scan_tail(struct mtd_info *mtd)
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pr_warn("No ECC functions supplied; hardware ECC not possible\n");
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BUG();
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}
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- if (!ecc->read_page)
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+
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+ if (!ecc->read_page) {
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ecc->read_page = nand_read_page_hwecc_oob_first;
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+ if (!ecc->read_subpage) {
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+ ecc->read_subpage = nand_read_subpage_hwecc_oob_first;
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+ chip->options |= NAND_SUBPAGE_READ;
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+ }
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+ }
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case NAND_ECC_HW:
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/* Use standard hwecc read page function? */
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