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61 lines
1.8 KiB
Diff
61 lines
1.8 KiB
Diff
From 28ec0b7e48bb27435a8b3134019b88628faf497f Mon Sep 17 00:00:00 2001
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From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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Date: Tue, 11 Dec 2018 17:37:28 +0800
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Subject: [PATCH 4/6] dt-bindings: ARM: MediaTek: Document devicetree bindings
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for SPI NAND interface
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Change-Id: I9ece142055ae27100da95826fb3ea1960c2994e6
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Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
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---
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.../devicetree/bindings/spi/spi-mtk-snfi.txt | 44 +++++++++++++++++++
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1 file changed, 44 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/spi/spi-mtk-snfi.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/spi/spi-mtk-snfi.txt
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@@ -0,0 +1,44 @@
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+MediaTek SoCs SPI NAND FLASH interface (SNFI) DT binding
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+
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+This file documents the device tree bindings for MTK SoCs SPI NAND controller.
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+Note that Parallel Nand and SPI NAND is alternative on MTK SoCs.
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+
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+Required properties:
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+- compatible: should be "mediatek,mt7622-snfi"
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+- reg: base physical address and size of SNFI.
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+- interrupts: interrupts of SNFI.
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+- clocks: SNFI required clocks.
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+- clock-names: SNFI clocks internal names.
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+- #address-cells: NAND chip index, should be 1.
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+- #size-cells: Should be 0.
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+
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+Example:
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+ snfi: spi@1100d000 {
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+ compatible = "mediatek,mt7622-snfi";
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+ reg = <0 0x1100d000 0 0x1000>;
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+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI_PD>,
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+ <&pericfg CLK_PERI_SNFI_PD>;
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+ clock-names = "nfi_clk", "spi_clk";
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+ ecc-engine = <&bch>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+Subnodes properties:
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+- Should use spi-nand framework, see Documentation/devicetree/bindings/mtd/spi-nand.txt
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+
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+Example:
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+&snfi {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&serial_nand_pins>;
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+ status = "okay";
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+
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+ spi_nand@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "spi-nand";
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+ spi-max-frequency = <104000000>;
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+ reg = <0>;
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+ };
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+};
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