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273 lines
8.8 KiB
Diff
273 lines
8.8 KiB
Diff
From 91eb47531421f0e8c9bc4594b4a7caa0e59dc83e Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Fri, 20 Mar 2020 12:01:19 +0100
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Subject: [PATCH] staging: mt7621-pci-phy: avoid to create to different phys
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for a dual port one
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This soc has two phy's for the pcie one of them using just a different
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register for settig it up but sharing all the rest of the config. Until
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now we was presenting this schema as three different phy's in the device
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tree using the 'phy-cells' node property to discriminate an index and
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setting up a complete phy for the dual port index. This sometimes worked
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properly but reconfiguring the same registers twice presents sometimes
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some unstable pcie links and the ports was not properly being detected.
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The problems only appears on hard resets and soft resets was properly
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working. Instead of having this schema just set two phy's in the device
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ree and use the 'phy-cells' property to say if the port has or not a dual
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port. Doing this configuration and set up becomes easier, LOC is decreased
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and the behaviour also gets deterministic with properly and stable pcie
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links in both hard and soft resets.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20200320110123.9907-2-sergio.paracuellos@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c | 144 ++++++++++--------------
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1 file changed, 59 insertions(+), 85 deletions(-)
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--- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
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+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
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@@ -78,31 +78,21 @@
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#define MAX_PHYS 2
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/**
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- * struct mt7621_pci_phy_instance - Mt7621 Pcie PHY device
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- * @phy: pointer to the kernel PHY device
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- * @port_base: base register
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- * @index: internal ID to identify the Mt7621 PCIe PHY
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- */
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-struct mt7621_pci_phy_instance {
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- struct phy *phy;
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- void __iomem *port_base;
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- u32 index;
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-};
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-
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-/**
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* struct mt7621_pci_phy - Mt7621 Pcie PHY core
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* @dev: pointer to device
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* @regmap: kernel regmap pointer
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- * @phys: pointer to Mt7621 PHY device
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- * @nphys: number of PHY devices for this core
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+ * @phy: pointer to the kernel PHY device
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+ * @port_base: base register
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+ * @has_dual_port: if the phy has dual ports.
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* @bypass_pipe_rst: mark if 'mt7621_bypass_pipe_rst'
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* needs to be executed. Depends on chip revision.
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*/
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struct mt7621_pci_phy {
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struct device *dev;
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struct regmap *regmap;
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- struct mt7621_pci_phy_instance **phys;
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- int nphys;
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+ struct phy *phy;
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+ void __iomem *port_base;
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+ bool has_dual_port;
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bool bypass_pipe_rst;
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};
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@@ -130,23 +120,23 @@ static inline void mt7621_phy_rmw(struct
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phy_write(phy, val, reg);
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}
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-static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy,
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- struct mt7621_pci_phy_instance *instance)
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+static void mt7621_bypass_pipe_rst(struct mt7621_pci_phy *phy)
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{
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- u32 offset = (instance->index != 1) ?
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- RG_PE1_PIPE_REG : RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH;
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+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_RST);
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+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG, 0, RG_PE1_PIPE_CMD_FRC);
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- mt7621_phy_rmw(phy, offset,
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- RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC,
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- RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
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+ if (phy->has_dual_port) {
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+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
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+ 0, RG_PE1_PIPE_RST);
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+ mt7621_phy_rmw(phy, RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH,
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+ 0, RG_PE1_PIPE_CMD_FRC);
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+ }
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}
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-static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy,
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- struct mt7621_pci_phy_instance *instance)
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+static void mt7621_set_phy_for_ssc(struct mt7621_pci_phy *phy)
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{
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struct device *dev = phy->dev;
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u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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- u32 offset;
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reg = (reg >> 6) & 0x7;
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/* Set PCIe Port PHY to disable SSC */
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@@ -156,10 +146,13 @@ static void mt7621_set_phy_for_ssc(struc
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RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE_VAL(0x00));
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/* disable port */
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- offset = (instance->index != 1) ?
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- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
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- mt7621_phy_rmw(phy, offset,
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- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG,
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+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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+
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+ if (phy->has_dual_port) {
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+ mt7621_phy_rmw(phy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
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+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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+ }
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if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
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/* Set Pre-divider ratio (for host mode) */
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@@ -223,43 +216,44 @@ static void mt7621_set_phy_for_ssc(struc
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static int mt7621_pci_phy_init(struct phy *phy)
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{
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- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
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- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
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+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
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if (mphy->bypass_pipe_rst)
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- mt7621_bypass_pipe_rst(mphy, instance);
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+ mt7621_bypass_pipe_rst(mphy);
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- mt7621_set_phy_for_ssc(mphy, instance);
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+ mt7621_set_phy_for_ssc(mphy);
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return 0;
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}
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static int mt7621_pci_phy_power_on(struct phy *phy)
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{
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- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
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- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
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- u32 offset = (instance->index != 1) ?
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- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
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+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
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/* Enable PHY and disable force mode */
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- mt7621_phy_rmw(mphy, offset,
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- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN,
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- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
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+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
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+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
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+
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+ if (mphy->has_dual_port) {
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+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
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+ RG_PE1_FRC_PHY_EN, RG_PE1_PHY_EN);
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+ }
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return 0;
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}
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static int mt7621_pci_phy_power_off(struct phy *phy)
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{
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- struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
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- struct mt7621_pci_phy *mphy = dev_get_drvdata(phy->dev.parent);
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- u32 offset = (instance->index != 1) ?
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- RG_PE1_FRC_PHY_REG : RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
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+ struct mt7621_pci_phy *mphy = phy_get_drvdata(phy);
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/* Disable PHY */
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- mt7621_phy_rmw(mphy, offset,
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- RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN,
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- RG_PE1_FRC_PHY_EN);
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+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG,
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+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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+
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+ if (mphy->has_dual_port) {
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+ mt7621_phy_rmw(mphy, RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH,
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+ RG_PE1_PHY_EN, RG_PE1_FRC_PHY_EN);
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+ }
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return 0;
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}
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@@ -282,13 +276,15 @@ static struct phy *mt7621_pcie_phy_of_xl
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{
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struct mt7621_pci_phy *mt7621_phy = dev_get_drvdata(dev);
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- if (args->args_count == 0)
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- return mt7621_phy->phys[0]->phy;
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-
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if (WARN_ON(args->args[0] >= MAX_PHYS))
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return ERR_PTR(-ENODEV);
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- return mt7621_phy->phys[args->args[0]]->phy;
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+ mt7621_phy->has_dual_port = args->args[0];
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+
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+ dev_info(dev, "PHY for 0x%08x (dual port = %d)\n",
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+ (unsigned int)mt7621_phy->port_base, mt7621_phy->has_dual_port);
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+
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+ return mt7621_phy->phy;
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}
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static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
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@@ -309,19 +305,11 @@ static int mt7621_pci_phy_probe(struct p
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struct phy_provider *provider;
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struct mt7621_pci_phy *phy;
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struct resource *res;
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- int port;
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- void __iomem *port_base;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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- phy->nphys = MAX_PHYS;
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- phy->phys = devm_kcalloc(dev, phy->nphys,
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- sizeof(*phy->phys), GFP_KERNEL);
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- if (!phy->phys)
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- return -ENOMEM;
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-
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attr = soc_device_match(mt7621_pci_quirks_match);
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if (attr)
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phy->bypass_pipe_rst = true;
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@@ -335,39 +323,25 @@ static int mt7621_pci_phy_probe(struct p
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return -ENXIO;
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}
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- port_base = devm_ioremap_resource(dev, res);
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- if (IS_ERR(port_base)) {
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+ phy->port_base = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(phy->port_base)) {
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dev_err(dev, "failed to remap phy regs\n");
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- return PTR_ERR(port_base);
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+ return PTR_ERR(phy->port_base);
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}
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- phy->regmap = devm_regmap_init_mmio(phy->dev, port_base,
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+ phy->regmap = devm_regmap_init_mmio(phy->dev, phy->port_base,
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&mt7621_pci_phy_regmap_config);
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if (IS_ERR(phy->regmap))
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return PTR_ERR(phy->regmap);
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- for (port = 0; port < MAX_PHYS; port++) {
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- struct mt7621_pci_phy_instance *instance;
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- struct phy *pphy;
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-
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- instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
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- if (!instance)
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- return -ENOMEM;
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-
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- phy->phys[port] = instance;
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-
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- pphy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
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- if (IS_ERR(phy)) {
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- dev_err(dev, "failed to create phy\n");
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- return PTR_ERR(phy);
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- }
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-
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- instance->port_base = port_base;
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- instance->phy = pphy;
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- instance->index = port;
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- phy_set_drvdata(pphy, instance);
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+ phy->phy = devm_phy_create(dev, dev->of_node, &mt7621_pci_phy_ops);
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+ if (IS_ERR(phy)) {
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+ dev_err(dev, "failed to create phy\n");
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+ return PTR_ERR(phy);
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}
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+ phy_set_drvdata(phy->phy, phy);
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+
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provider = devm_of_phy_provider_register(dev, mt7621_pcie_phy_of_xlate);
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return PTR_ERR_OR_ZERO(provider);
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