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90 lines
2.1 KiB
C
90 lines
2.1 KiB
C
/*
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* Ralink RT305x SoC specific setup
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/mips_machine.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/rt305x.h>
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#include <asm/mach-ralink/rt305x_regs.h>
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#include "common.h"
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static void rt305x_restart(char *command)
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{
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rt305x_sysc_wr(RT305X_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
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while (1)
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if (cpu_wait)
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cpu_wait();
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}
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static void rt305x_halt(void)
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{
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while (1)
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if (cpu_wait)
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cpu_wait();
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}
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unsigned int __cpuinit get_c0_compare_irq(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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void __init ramips_soc_setup(void)
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{
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struct clk *clk;
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rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
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rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);
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rt305x_detect_sys_type();
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rt305x_clocks_init();
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clk = clk_get(NULL, "cpu");
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if (IS_ERR(clk))
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panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
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printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
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clk_get_rate(clk) / 1000000,
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(clk_get_rate(clk) % 1000000) * 100 / 1000000);
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_machine_restart = rt305x_restart;
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_machine_halt = rt305x_halt;
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pm_power_off = rt305x_halt;
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clk = clk_get(NULL, "uart");
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if (IS_ERR(clk))
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panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
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ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk),
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RT305X_INTC_IRQ_UART0);
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ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk),
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RT305X_INTC_IRQ_UART1);
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}
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void __init plat_time_init(void)
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{
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struct clk *clk;
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clk = clk_get(NULL, "cpu");
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if (IS_ERR(clk))
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panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
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mips_hpt_frequency = clk_get_rate(clk) / 2;
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}
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