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151 lines
4.8 KiB
C
151 lines
4.8 KiB
C
/*
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* Ralink RT305 SoC register definitions
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _RT305X_REGS_H_
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#define _RT305X_REGS_H_
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#include <linux/bitops.h>
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#define RT305X_SDRAM_BASE 0x00000000
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#define RT305X_SYSC_BASE 0x10000000
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#define RT305X_TIMER_BASE 0x10000100
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#define RT305X_INTC_BASE 0x10000200
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#define RT305X_MEMC_BASE 0x10000300
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#define RT305X_PCM_BASE 0x10000400
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#define RT305X_UART0_BASE 0x10000500
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#define RT305X_PIO_BASE 0x10000600
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#define RT305X_GDMA_BASE 0x10000700
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#define RT305X_NANDC_BASE 0x10000800
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#define RT305X_I2C_BASE 0x10000900
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#define RT305X_I2S_BASE 0x10000a00
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#define RT305X_SPI_BASE 0x10000b00
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#define RT305X_UART1_BASE 0x10000c00
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#define RT305X_FE_BASE 0x10100000
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#define RT305X_SWITCH_BASE 0x10110000
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#define RT305X_WMAC_BASE 0x10180000
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#define RT305X_OTG_BASE 0x101c0000
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#define RT305X_ROM_BASE 0x00400000
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#define RT305X_FLASH1_BASE 0x1b000000
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#define RT305X_FLASH0_BASE 0x1f000000
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#define RT305X_SYSC_SIZE 0x100
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#define RT305X_TIMER_SIZE 0x100
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#define RT305X_INTC_SIZE 0x100
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#define RT305X_MEMC_SIZE 0x100
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#define RT305X_UART0_SIZE 0x100
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#define RT305X_PIO_SIZE 0x100
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#define RT305X_UART1_SIZE 0x100
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#define RT305X_SPI_SIZE 0x100
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#define RT305X_FLASH1_SIZE (16 * 1024 * 1024)
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#define RT305X_FLASH0_SIZE (8 * 1024 * 1024)
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/* SYSC registers */
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#define SYSC_REG_CHIP_NAME0 0x000 /* Chip Name 0 */
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#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
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#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
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#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
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#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
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#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
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#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
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#define SYSC_REG_IA_ADDRESS 0x310 /* Illegal Access Address */
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#define SYSC_REG_IA_TYPE 0x314 /* Illegal Access Type */
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#define CHIP_ID_ID_MASK 0xff
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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#define SYSTEM_CONFIG_CPUCLK_SHIFT 18
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#define SYSTEM_CONFIG_CPUCLK_MASK 0x1
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#define SYSTEM_CONFIG_CPUCLK_320 0x0
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#define SYSTEM_CONFIG_CPUCLK_384 0x1
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_SHIFT 2
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_MASK 0x3
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_NORMAL 0
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_WDT 1
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#define SYSTEM_CONFIG_SRAM_CS0_MODE_BTCOEX 2
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#define RT305X_GPIO_MODE_I2C BIT(0)
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#define RT305X_GPIO_MODE_SPI BIT(1)
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#define RT305X_GPIO_MODE_UART0_SHIFT 2
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#define RT305X_GPIO_MODE_UART0_MASK 0x7
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#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
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#define RT305X_GPIO_MODE_UARTF 0x0
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#define RT305X_GPIO_MODE_PCM_UARTF 0x1
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#define RT305X_GPIO_MODE_PCM_I2S 0x2
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#define RT305X_GPIO_MODE_I2S_UARTF 0x3
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#define RT305X_GPIO_MODE_PCM_GPIO 0x4
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#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
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#define RT305X_GPIO_MODE_GPIO_I2S 0x6
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#define RT305X_GPIO_MODE_GPIO 0x7
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#define RT305X_GPIO_MODE_UART1 BIT(5)
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#define RT305X_GPIO_MODE_JTAG BIT(6)
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#define RT305X_GPIO_MODE_MDIO BIT(7)
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#define RT305X_GPIO_MODE_SDRAM BIT(8)
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#define RT305X_GPIO_MODE_RGMII BIT(9)
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#define RT305X_RESET_SYSTEM BIT(0)
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#define RT305X_RESET_TIMER BIT(8)
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#define RT305X_RESET_INTC BIT(9)
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#define RT305X_RESET_MEMC BIT(10)
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#define RT305X_RESET_PCM BIT(11)
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#define RT305X_RESET_UART0 BIT(12)
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#define RT305X_RESET_PIO BIT(13)
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#define RT305X_RESET_DMA BIT(14)
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#define RT305X_RESET_I2C BIT(16)
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#define RT305X_RESET_I2S BIT(17)
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#define RT305X_RESET_SPI BIT(18)
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#define RT305X_RESET_UART1 BIT(19)
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#define RT305X_RESET_WNIC BIT(20)
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#define RT305X_RESET_FE BIT(21)
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#define RT305X_RESET_OTG BIT(22)
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#define RT305X_RESET_ESW BIT(23)
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#define RT305X_INTC_INT_SYSCTL BIT(0)
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#define RT305X_INTC_INT_TIMER0 BIT(1)
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#define RT305X_INTC_INT_TIMER1 BIT(2)
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#define RT305X_INTC_INT_IA BIT(3)
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#define RT305X_INTC_INT_PCM BIT(4)
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#define RT305X_INTC_INT_UART0 BIT(5)
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#define RT305X_INTC_INT_PIO BIT(6)
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#define RT305X_INTC_INT_DMA BIT(7)
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#define RT305X_INTC_INT_NAND BIT(8)
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#define RT305X_INTC_INT_PERFC BIT(9)
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#define RT305X_INTC_INT_I2S BIT(10)
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#define RT305X_INTC_INT_UART1 BIT(12)
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#define RT305X_INTC_INT_ESW BIT(17)
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#define RT305X_INTC_INT_OTG BIT(18)
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#define RT305X_INTC_INT_GLOBAL BIT(31)
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/* MEMC registers */
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#define MEMC_REG_SDRAM_CFG0 0x00
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#define MEMC_REG_SDRAM_CFG1 0x04
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#define MEMC_REG_FLASH_CFG0 0x08
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#define MEMC_REG_FLASH_CFG1 0x0c
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#define MEMC_REG_IA_ADDR 0x10
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#define MEMC_REG_IA_TYPE 0x14
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#define FLASH_CFG_WIDTH_SHIFT 26
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#define FLASH_CFG_WIDTH_MASK 0x3
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#define FLASH_CFG_WIDTH_8BIT 0x0
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#define FLASH_CFG_WIDTH_16BIT 0x1
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#define FLASH_CFG_WIDTH_32BIT 0x2
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/* UART registers */
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#define UART_REG_RX 0
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#define UART_REG_TX 1
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#define UART_REG_IER 2
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#define UART_REG_IIR 3
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#define UART_REG_FCR 4
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#define UART_REG_LCR 5
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#define UART_REG_MCR 6
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#define UART_REG_LSR 7
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#endif /* _RT305X_REGS_H_ */
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