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136 lines
4.3 KiB
Diff
136 lines
4.3 KiB
Diff
From 2e891d3d62f5fd51e33ae6e614198ce0b3b48e95 Mon Sep 17 00:00:00 2001
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From: Viorel Suman <viorel.suman@nxp.com>
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Date: Wed, 6 Jun 2018 13:36:20 +0300
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Subject: [PATCH] MLK-18534-1: ASoC: fsl: sai: introduce 1:1 bclk:mclk ratio
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support
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Since IP version 3.01 (845s) SAI has support for 1:1
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bclk:mclk ratio.
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Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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---
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sound/soc/fsl/fsl_sai.c | 69 +++++++++++++++++++++++++------------------------
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sound/soc/fsl/fsl_sai.h | 2 +-
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2 files changed, 36 insertions(+), 35 deletions(-)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -471,7 +471,8 @@ static int fsl_sai_set_bclk(struct snd_s
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
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unsigned char offset = sai->soc->reg_offset;
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unsigned long clk_rate;
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- u32 savediv = 0, ratio, savesub = freq;
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+ unsigned int reg = 0;
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+ u32 ratio, savesub = freq, saveratio = 0, savediv = 0;
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u32 id;
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int ret = 0;
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@@ -479,6 +480,8 @@ static int fsl_sai_set_bclk(struct snd_s
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if (sai->slave_mode[tx])
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return 0;
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+ fsl_sai_check_ver(dai);
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+
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for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
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clk_rate = clk_get_rate(sai->mclk_clk[id]);
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if (!clk_rate)
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@@ -499,22 +502,21 @@ static int fsl_sai_set_bclk(struct snd_s
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"ratio %d for freq %dHz based on clock %ldHz\n",
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ratio, freq, clk_rate);
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- if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
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- ratio /= 2;
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- else
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- continue;
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+ if ((ratio % 2 == 0 && ratio >= 2 && ratio <= 512) ||
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+ (ratio == 1 && sai->verid.id >= FSL_SAI_VERID_0301)) {
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- if (ret < savesub) {
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- savediv = ratio;
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- sai->mclk_id[tx] = id;
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- savesub = ret;
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- }
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+ if (ret < savesub) {
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+ saveratio = ratio;
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+ sai->mclk_id[tx] = id;
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+ savesub = ret;
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+ }
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- if (ret == 0)
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- break;
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+ if (ret == 0)
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+ break;
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+ }
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}
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- if (savediv == 0) {
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+ if (saveratio == 0) {
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dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
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tx ? 'T' : 'R', freq);
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return -EINVAL;
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@@ -530,33 +532,32 @@ static int fsl_sai_set_bclk(struct snd_s
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* 4) For Tx and Rx are both Synchronous with another SAI, we just
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* ignore it.
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*/
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- if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
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- (!tx && !sai->synchronous[RX])) {
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- regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset),
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- FSL_SAI_CR2_MSEL_MASK,
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- FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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- regmap_update_bits(sai->regmap, FSL_SAI_RCR2(offset),
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- FSL_SAI_CR2_DIV_MASK, savediv - 1);
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- } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
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- (tx && !sai->synchronous[TX])) {
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- regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset),
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- FSL_SAI_CR2_MSEL_MASK,
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- FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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- regmap_update_bits(sai->regmap, FSL_SAI_TCR2(offset),
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- FSL_SAI_CR2_DIV_MASK, savediv - 1);
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+ if ((!tx || sai->synchronous[TX]) && !sai->synchronous[RX])
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+ reg = FSL_SAI_RCR2(offset);
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+ else if ((tx || sai->synchronous[RX]) && !sai->synchronous[TX])
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+ reg = FSL_SAI_TCR2(offset);
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+
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+ if (reg) {
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+ regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
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+ FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
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+
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+ savediv = (saveratio == 1 ? 0 : (saveratio >> 1) - 1);
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+ regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK, savediv);
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+
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+ if (sai->verid.id >= FSL_SAI_VERID_0301) {
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+ regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_BYP,
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+ (saveratio == 1 ? FSL_SAI_CR2_BYP : 0));
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+ }
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}
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- fsl_sai_check_ver(dai);
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- switch (sai->verid.id) {
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- case FSL_SAI_VERID_0301:
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+ if (sai->verid.id >= FSL_SAI_VERID_0301) {
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/* SAI is in master mode at this point, so enable MCLK */
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regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
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- FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
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- break;
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+ FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
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}
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- dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
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- sai->mclk_id[tx], savediv, savesub);
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+ dev_dbg(dai->dev, "best fit: clock id=%d, ratio=%d, deviation=%d\n",
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+ sai->mclk_id[tx], saveratio, savesub);
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return 0;
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}
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--- a/sound/soc/fsl/fsl_sai.h
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+++ b/sound/soc/fsl/fsl_sai.h
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@@ -122,7 +122,7 @@
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#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
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#define FSL_SAI_CR2_BCP BIT(25)
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#define FSL_SAI_CR2_BCD_MSTR BIT(24)
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-#define FSL_SAI_CR2_BCBP BIT(23) /* BCLK bypass */
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+#define FSL_SAI_CR2_BYP BIT(23) /* BCLK bypass */
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#define FSL_SAI_CR2_DIV_MASK 0xff
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/* SAI Transmit and Receive Configuration 3 Register */
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