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98 lines
3.8 KiB
Diff
98 lines
3.8 KiB
Diff
From 2e4c0c429526d88b96319d7bb08c51bfa70f6e27 Mon Sep 17 00:00:00 2001
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From: Bhupesh Sharma <bhsharma@redhat.com>
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Date: Fri, 29 Nov 2019 01:55:13 +0530
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Subject: [PATCH] LF-419 arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo
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vabits_actual variable on arm64 indicates the actual VA space size,
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and allows a single binary to support both 48-bit and 52-bit VA
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spaces.
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If the ARMv8.2-LVA optional feature is present, and we are running
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with a 64KB page size; then it is possible to use 52-bits of address
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space for both userspace and kernel addresses. However, any kernel
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binary that supports 52-bit must also be able to fall back to 48-bit
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at early boot time if the hardware feature is not present.
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Since TCR_EL1.T1SZ indicates the size offset of the memory region
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addressed by TTBR1_EL1 (and hence can be used for determining the
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vabits_actual value) it makes more sense to export the same in
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vmcoreinfo rather than vabits_actual variable, as the name of the
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variable can change in future kernel versions, but the architectural
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constructs like TCR_EL1.T1SZ can be used better to indicate intended
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specific fields to user-space.
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User-space utilities like makedumpfile and crash-utility, need to
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read/write this value from/to vmcoreinfo for determining if a virtual
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address lies in the linear map range.
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The user-space computation for determining whether an address lies in
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the linear map range is the same as we have in kernel-space:
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#define __is_lm_address(addr) (!(((u64)addr) & BIT(vabits_actual - 1)))
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I have sent out user-space patches for makedumpfile and crash-utility
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to add features for obtaining vabits_actual value from TCR_EL1.T1SZ (see
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[0] and [1]).
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Akashi reported that he was able to use this patchset and the user-space
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changes to get user-space working fine with the 52-bit kernel VA
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changes (see [2]).
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[0]. http://lists.infradead.org/pipermail/kexec/2019-November/023966.html
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[1]. http://lists.infradead.org/pipermail/kexec/2019-November/024006.html
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[2]. http://lists.infradead.org/pipermail/kexec/2019-November/023992.html
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Cc: James Morse <james.morse@arm.com>
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Cc: Mark Rutland <mark.rutland@arm.com>
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Cc: Will Deacon <will@kernel.org>
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Cc: Steve Capper <steve.capper@arm.com>
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Cc: Catalin Marinas <catalin.marinas@arm.com>
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Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Cc: Dave Anderson <anderson@redhat.com>
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Cc: Kazuhito Hagio <k-hagio@ab.jp.nec.com>
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Cc: linux-arm-kernel@lists.infradead.org
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Cc: linux-kernel@vger.kernel.org
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Cc: kexec@lists.infradead.org
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Signed-off-by: Bhupesh Sharma <bhsharma@redhat.com>
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Tested-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
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Acked-by: Li Yang <leoyang.li@nxp.com>
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---
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arch/arm64/include/asm/pgtable-hwdef.h | 1 +
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arch/arm64/kernel/crash_core.c | 9 +++++++++
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2 files changed, 10 insertions(+)
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--- a/arch/arm64/include/asm/pgtable-hwdef.h
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+++ b/arch/arm64/include/asm/pgtable-hwdef.h
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@@ -215,6 +215,7 @@
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#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x))
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#define TCR_TxSZ_WIDTH 6
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#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
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+#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
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#define TCR_EPD0_SHIFT 7
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#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
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--- a/arch/arm64/kernel/crash_core.c
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+++ b/arch/arm64/kernel/crash_core.c
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@@ -7,6 +7,13 @@
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#include <linux/crash_core.h>
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#include <asm/memory.h>
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+static inline u64 get_tcr_el1_t1sz(void);
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+
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+static inline u64 get_tcr_el1_t1sz(void)
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+{
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+ return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET;
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+}
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+
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void arch_crash_save_vmcoreinfo(void)
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{
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VMCOREINFO_NUMBER(VA_BITS);
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@@ -15,5 +22,7 @@ void arch_crash_save_vmcoreinfo(void)
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kimage_voffset);
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vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n",
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PHYS_OFFSET);
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+ vmcoreinfo_append_str("NUMBER(tcr_el1_t1sz)=0x%llx\n",
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+ get_tcr_el1_t1sz());
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vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset());
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}
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