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89 lines
2.5 KiB
Diff
89 lines
2.5 KiB
Diff
From 1355a27c85ae89225e738b9016656a406542ed1b Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 20 Jun 2011 21:26:10 +0200
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Subject: [PATCH 13/27] MIPS: ath79: add AR933X specific USB platform device registration
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Also select the USB_ARCH_HAS_EHCI symbol in order to make the
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EHCI driver available.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: Kathy Giori <kgiori@qca.qualcomm.com>
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Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
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Patchwork: https://patchwork.linux-mips.org/patch/2527/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/ath79/Kconfig | 1 +
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arch/mips/ath79/dev-usb.c | 19 +++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 +++++++
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3 files changed, 27 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -42,6 +42,7 @@ config SOC_AR913X
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def_bool n
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config SOC_AR933X
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+ select USB_ARCH_HAS_EHCI
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def_bool n
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config ATH79_DEV_AR913X_WMAC
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--- a/arch/mips/ath79/dev-usb.c
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+++ b/arch/mips/ath79/dev-usb.c
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@@ -163,6 +163,23 @@ static void __init ar913x_usb_setup(void
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platform_device_register(&ath79_ehci_device);
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}
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+static void __init ar933x_usb_setup(void)
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+{
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+ ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
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+ mdelay(10);
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+
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+ ath79_device_reset_clear(AR933X_RESET_USB_HOST);
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+ mdelay(10);
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+
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+ ath79_device_reset_clear(AR933X_RESET_USB_PHY);
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+ mdelay(10);
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+
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+ ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
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+ ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
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+ ath79_ehci_device.name = "ar933x-ehci";
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+ platform_device_register(&ath79_ehci_device);
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+}
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+
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void __init ath79_register_usb(void)
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{
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if (soc_is_ar71xx())
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@@ -173,6 +190,8 @@ void __init ath79_register_usb(void)
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ar724x_usb_setup();
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else if (soc_is_ar913x())
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ar913x_usb_setup();
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+ else if (soc_is_ar933x())
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+ ar933x_usb_setup();
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else
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BUG();
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -56,6 +56,9 @@
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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+#define AR933X_EHCI_BASE 0x1b000000
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+#define AR933X_EHCI_SIZE 0x1000
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+
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/*
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* DDR_CTRL block
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*/
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@@ -230,6 +233,10 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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+#define AR933X_RESET_USB_HOST BIT(5)
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+#define AR933X_RESET_USB_PHY BIT(4)
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+#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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+
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define REV_ID_MAJOR_MASK 0xfff0
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