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627 lines
16 KiB
Diff
627 lines
16 KiB
Diff
From 2eccfcf4c5c50b412a0859a345d8d28fc043956b Mon Sep 17 00:00:00 2001
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From: Mike Lockwood <lockwood@android.com>
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Date: Thu, 7 Feb 2008 07:47:30 -0500
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Subject: [PATCH 124/134] [ARM] goldfish: mmc: goldfish MMC driver building and runnning in 2.6.27.
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Signed-off-by: Mike A. Chan <mikechan@google.com>
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---
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drivers/mmc/host/Kconfig | 8 +
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drivers/mmc/host/Makefile | 1 +
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drivers/mmc/host/goldfish.c | 583 +++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 592 insertions(+), 0 deletions(-)
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create mode 100644 drivers/mmc/host/goldfish.c
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--- a/drivers/mmc/host/Kconfig
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+++ b/drivers/mmc/host/Kconfig
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@@ -200,6 +200,14 @@ config MMC_MVSDIO
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To compile this driver as a module, choose M here: the
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module will be called mvsdio.
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+config MMC_GOLDFISH
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+ tristate "goldfish qemu Multimedia Card Interface support"
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+ depends on ARCH_GOLDFISH
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+ help
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+ This selects the Goldfish Multimedia card Interface emulation.
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+
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+ If unsure, say N.
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+
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config MMC_SPI
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tristate "MMC/SD/SDIO over SPI"
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depends on SPI_MASTER && !HIGHMEM && HAS_DMA
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--- a/drivers/mmc/host/Makefile
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+++ b/drivers/mmc/host/Makefile
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@@ -26,6 +26,7 @@ obj-$(CONFIG_MMC_SPI) += mmc_spi.o
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ifeq ($(CONFIG_OF),y)
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obj-$(CONFIG_MMC_SPI) += of_mmc_spi.o
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endif
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+obj-$(CONFIG_MMC_GOLDFISH) += goldfish.o
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obj-$(CONFIG_MMC_S3C) += s3cmci.o
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obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o
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obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
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--- /dev/null
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+++ b/drivers/mmc/host/goldfish.c
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@@ -0,0 +1,583 @@
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+/*
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+ * linux/drivers/media/mmc/goldfish.c
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+ *
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+ * Copyright 2007, Google Inc.
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+ *
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+ * based on omap.c driver, which was
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+ * Copyright (C) 2004 Nokia Corporation
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+ * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
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+ * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
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+ * Other hacks (DMA, SD, etc) by David Brownell
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/major.h>
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/interrupt.h>
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+
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+#include <linux/kernel.h>
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+#include <linux/fs.h>
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+#include <linux/errno.h>
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+#include <linux/hdreg.h>
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+#include <linux/kdev_t.h>
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+#include <linux/blkdev.h>
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+#include <linux/mutex.h>
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+#include <linux/scatterlist.h>
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+#include <linux/mmc/mmc.h>
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+#include <linux/mmc/sdio.h>
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+#include <linux/mmc/host.h>
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+#include <linux/mmc/card.h>
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+
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+#include <linux/moduleparam.h>
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+#include <linux/init.h>
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+#include <linux/ioport.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/delay.h>
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+#include <linux/spinlock.h>
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+#include <linux/timer.h>
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+#include <linux/clk.h>
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+
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+#include <asm/io.h>
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+#include <asm/irq.h>
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+#include <asm/scatterlist.h>
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+#include <asm/mach-types.h>
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+
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+
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+#include <asm/types.h>
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+#include <asm/io.h>
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+#include <asm/uaccess.h>
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+
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+#define DRIVER_NAME "goldfish_mmc"
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+
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+#define BUFFER_SIZE 16384
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+
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+#define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
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+#define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
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+
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+
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+enum {
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+ /* status register */
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+ MMC_INT_STATUS = 0x00,
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+ /* set this to enable IRQ */
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+ MMC_INT_ENABLE = 0x04,
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+ /* set this to specify buffer address */
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+ MMC_SET_BUFFER = 0x08,
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+
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+ /* MMC command number */
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+ MMC_CMD = 0x0C,
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+
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+ /* MMC argument */
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+ MMC_ARG = 0x10,
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+
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+ /* MMC response (or R2 bits 0 - 31) */
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+ MMC_RESP_0 = 0x14,
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+
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+ /* MMC R2 response bits 32 - 63 */
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+ MMC_RESP_1 = 0x18,
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+
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+ /* MMC R2 response bits 64 - 95 */
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+ MMC_RESP_2 = 0x1C,
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+
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+ /* MMC R2 response bits 96 - 127 */
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+ MMC_RESP_3 = 0x20,
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+
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+ MMC_BLOCK_LENGTH = 0x24,
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+ MMC_BLOCK_COUNT = 0x28,
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+
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+ /* MMC state flags */
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+ MMC_STATE = 0x2C,
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+
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+ /* MMC_INT_STATUS bits */
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+
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+ MMC_STAT_END_OF_CMD = 1U << 0,
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+ MMC_STAT_END_OF_DATA = 1U << 1,
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+ MMC_STAT_STATE_CHANGE = 1U << 2,
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+
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+ /* MMC_STATE bits */
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+ MMC_STATE_INSERTED = 1U << 0,
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+ MMC_STATE_READ_ONLY = 1U << 1,
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+};
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+
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+/*
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+ * Command types
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+ */
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+#define OMAP_MMC_CMDTYPE_BC 0
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+#define OMAP_MMC_CMDTYPE_BCR 1
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+#define OMAP_MMC_CMDTYPE_AC 2
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+#define OMAP_MMC_CMDTYPE_ADTC 3
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+
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+
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+struct goldfish_mmc_host {
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+ struct mmc_request * mrq;
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+ struct mmc_command * cmd;
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+ struct mmc_data * data;
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+ struct mmc_host * mmc;
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+ struct device * dev;
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+ unsigned char id; /* 16xx chips have 2 MMC blocks */
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+ void __iomem *virt_base;
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+ unsigned int phys_base;
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+ int irq;
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+ unsigned char bus_mode;
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+ unsigned char hw_bus_mode;
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+
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+ unsigned int sg_len;
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+ unsigned dma_done:1;
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+ unsigned dma_in_use:1;
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+
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+ struct work_struct switch_work;
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+ int switch_last_state;
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+
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+ uint32_t reg_base;
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+};
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+
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+static inline int
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+goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
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+{
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+ return 0;
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+}
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+
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+static ssize_t
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+goldfish_mmc_show_cover_switch(struct device *dev,
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+ struct device_attribute *attr, char *buf)
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+{
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+ struct goldfish_mmc_host *host = dev_get_drvdata(dev);
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+
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+ return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
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+ "closed");
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+}
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+
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+static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);
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+
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+static void
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+goldfish_mmc_start_command(struct goldfish_mmc_host *host, struct mmc_command *cmd)
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+{
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+ u32 cmdreg;
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+ u32 resptype;
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+ u32 cmdtype;
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+
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+ host->cmd = cmd;
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+
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+ resptype = 0;
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+ cmdtype = 0;
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+
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+ /* Our hardware needs to know exact type */
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+ switch (mmc_resp_type(cmd)) {
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+ case MMC_RSP_NONE:
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+ break;
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+ case MMC_RSP_R1:
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+ case MMC_RSP_R1B:
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+ /* resp 1, 1b, 6, 7 */
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+ resptype = 1;
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+ break;
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+ case MMC_RSP_R2:
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+ resptype = 2;
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+ break;
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+ case MMC_RSP_R3:
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+ resptype = 3;
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+ break;
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+ default:
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+ dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
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+ break;
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+ }
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+
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+ if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
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+ cmdtype = OMAP_MMC_CMDTYPE_ADTC;
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+ } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
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+ cmdtype = OMAP_MMC_CMDTYPE_BC;
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+ } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
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+ cmdtype = OMAP_MMC_CMDTYPE_BCR;
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+ } else {
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+ cmdtype = OMAP_MMC_CMDTYPE_AC;
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+ }
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+
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+ cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
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+
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+ if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
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+ cmdreg |= 1 << 6;
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+
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+ if (cmd->flags & MMC_RSP_BUSY)
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+ cmdreg |= 1 << 11;
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+
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+ if (host->data && !(host->data->flags & MMC_DATA_WRITE))
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+ cmdreg |= 1 << 15;
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+
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+ GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
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+ GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
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+}
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+
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+static void
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+goldfish_mmc_xfer_done(struct goldfish_mmc_host *host, struct mmc_data *data)
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+{
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+ if (host->dma_in_use) {
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+ enum dma_data_direction dma_data_dir;
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+
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+ if (data->flags & MMC_DATA_WRITE)
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+ dma_data_dir = DMA_TO_DEVICE;
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+ else
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+ dma_data_dir = DMA_FROM_DEVICE;
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+
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+ if (dma_data_dir == DMA_FROM_DEVICE) {
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+ // we don't really have DMA, so we need to copy from our platform driver buffer
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+ uint8_t* dest = (uint8_t *)sg_virt(data->sg);
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+ memcpy(dest, host->virt_base, data->sg->length);
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+ }
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+
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+ host->data->bytes_xfered += data->sg->length;
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+
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+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len, dma_data_dir);
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+ }
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+
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+ host->data = NULL;
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+ host->sg_len = 0;
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+
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+ /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
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+ * dozens of requests until the card finishes writing data.
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+ * It'd be cheaper to just wait till an EOFB interrupt arrives...
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+ */
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+
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+ if (!data->stop) {
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+ host->mrq = NULL;
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+ mmc_request_done(host->mmc, data->mrq);
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+ return;
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+ }
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+
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+ goldfish_mmc_start_command(host, data->stop);
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+}
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+
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+static void
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+goldfish_mmc_end_of_data(struct goldfish_mmc_host *host, struct mmc_data *data)
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+{
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+ if (!host->dma_in_use) {
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+ goldfish_mmc_xfer_done(host, data);
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+ return;
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+ }
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+ if (host->dma_done)
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+ goldfish_mmc_xfer_done(host, data);
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+}
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+
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+static void
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+goldfish_mmc_cmd_done(struct goldfish_mmc_host *host, struct mmc_command *cmd)
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+{
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+ host->cmd = NULL;
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+ if (cmd->flags & MMC_RSP_PRESENT) {
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+ if (cmd->flags & MMC_RSP_136) {
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+ /* response type 2 */
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+ cmd->resp[3] =
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+ GOLDFISH_MMC_READ(host, MMC_RESP_0);
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+ cmd->resp[2] =
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+ GOLDFISH_MMC_READ(host, MMC_RESP_1);
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+ cmd->resp[1] =
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+ GOLDFISH_MMC_READ(host, MMC_RESP_2);
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+ cmd->resp[0] =
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+ GOLDFISH_MMC_READ(host, MMC_RESP_3);
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+ } else {
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+ /* response types 1, 1b, 3, 4, 5, 6 */
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+ cmd->resp[0] =
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+ GOLDFISH_MMC_READ(host, MMC_RESP_0);
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+ }
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+ }
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+
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+ if (host->data == NULL || cmd->error) {
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+ host->mrq = NULL;
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+ mmc_request_done(host->mmc, cmd->mrq);
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+ }
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+}
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+
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+static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
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+{
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+ struct goldfish_mmc_host * host = (struct goldfish_mmc_host *)dev_id;
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+ u16 status;
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+ int end_command;
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+ int end_transfer;
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+ int transfer_error;
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+ int state_changed;
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+
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+ if (host->cmd == NULL && host->data == NULL) {
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+ status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
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+ dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
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+ if (status != 0) {
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+ GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
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+ GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
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+ }
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+ return IRQ_HANDLED;
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+ }
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+
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+ end_command = 0;
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+ end_transfer = 0;
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+ transfer_error = 0;
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+ state_changed = 0;
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+
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+ while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
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+ GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
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+
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+ if (status & MMC_STAT_END_OF_CMD) {
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+ end_command = 1;
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+ }
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+
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+ if (status & MMC_STAT_END_OF_DATA) {
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+ end_transfer = 1;
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+ }
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+ if (status & MMC_STAT_STATE_CHANGE) {
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+ state_changed = 1;
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+ }
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+ }
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+
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+ if (end_command) {
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+ goldfish_mmc_cmd_done(host, host->cmd);
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+ }
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+ if (transfer_error)
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+ goldfish_mmc_xfer_done(host, host->data);
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+ else if (end_transfer) {
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+ host->dma_done = 1;
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+ goldfish_mmc_end_of_data(host, host->data);
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+ }
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+ if (state_changed) {
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+ schedule_work(&host->switch_work);
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+ }
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+
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+ return IRQ_HANDLED;
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+}
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+
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+
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+static void goldfish_mmc_switch_handler(struct work_struct *work)
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+{
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+/*
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+ struct goldfish_mmc_host *host = container_of(work, struct goldfish_mmc_host, switch_work);
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+ struct mmc_card *card;
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+ static int complained = 0;
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+ int cards = 0, cover_open;
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+
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+ cover_open = goldfish_mmc_cover_is_open(host);
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+ if (cover_open != host->switch_last_state) {
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+ kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
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+ host->switch_last_state = cover_open;
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+ }
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+ mmc_detect_change(host->mmc, 0);
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+ list_for_each_entry(card, &host->mmc->cards, node) {
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+ if (mmc_card_present(card))
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+ cards++;
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+ }
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+ if (goldfish_mmc_cover_is_open(host)) {
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+ if (!complained) {
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+ dev_info(mmc_dev(host->mmc), "cover is open\n");
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+ complained = 1;
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+ }
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+ } else {
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+ complained = 0;
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+ }
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+*/
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+}
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+
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+
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+static void
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+goldfish_mmc_prepare_data(struct goldfish_mmc_host *host, struct mmc_request *req)
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+{
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+ struct mmc_data *data = req->data;
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+ int block_size;
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+ unsigned sg_len;
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+ enum dma_data_direction dma_data_dir;
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+
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+ host->data = data;
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+ if (data == NULL) {
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+ GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
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+ GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
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+ host->dma_in_use = 0;
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+ return;
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+ }
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+
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+ block_size = data->blksz;
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+
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+ GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
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+ GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);
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+
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+ /* cope with calling layer confusion; it issues "single
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+ * block" writes using multi-block scatterlists.
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+ */
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+ sg_len = (data->blocks == 1) ? 1 : data->sg_len;
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+
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+ if (data->flags & MMC_DATA_WRITE)
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+ dma_data_dir = DMA_TO_DEVICE;
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+ else
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+ dma_data_dir = DMA_FROM_DEVICE;
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+
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+ host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
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+ sg_len, dma_data_dir);
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+ host->dma_done = 0;
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+ host->dma_in_use = 1;
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+
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+ if (dma_data_dir == DMA_TO_DEVICE) {
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+ // we don't really have DMA, so we need to copy to our platform driver buffer
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+ const uint8_t* src = (uint8_t *)sg_virt(data->sg);
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+ memcpy(host->virt_base, src, data->sg->length);
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+ }
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+}
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+
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+static void goldfish_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
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+{
|
|
+ struct goldfish_mmc_host *host = mmc_priv(mmc);
|
|
+
|
|
+ WARN_ON(host->mrq != NULL);
|
|
+
|
|
+ host->mrq = req;
|
|
+ goldfish_mmc_prepare_data(host, req);
|
|
+ goldfish_mmc_start_command(host, req->cmd);
|
|
+
|
|
+ /* this is to avoid accidentally being detected as an SDIO card in mmc_attach_sdio() */
|
|
+ if (req->cmd->opcode == SD_IO_SEND_OP_COND &&
|
|
+ req->cmd->flags == (MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR)) {
|
|
+ req->cmd->error = -EINVAL;
|
|
+ }
|
|
+}
|
|
+
|
|
+static void goldfish_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
+{
|
|
+ struct goldfish_mmc_host *host = mmc_priv(mmc);
|
|
+
|
|
+ host->bus_mode = ios->bus_mode;
|
|
+ host->hw_bus_mode = host->bus_mode;
|
|
+}
|
|
+
|
|
+static int goldfish_mmc_get_ro(struct mmc_host *mmc)
|
|
+{
|
|
+ uint32_t state;
|
|
+ struct goldfish_mmc_host *host = mmc_priv(mmc);
|
|
+
|
|
+ state = GOLDFISH_MMC_READ(host, MMC_STATE);
|
|
+ return ((state & MMC_STATE_READ_ONLY) != 0);
|
|
+}
|
|
+
|
|
+static const struct mmc_host_ops goldfish_mmc_ops = {
|
|
+ .request = goldfish_mmc_request,
|
|
+ .set_ios = goldfish_mmc_set_ios,
|
|
+ .get_ro = goldfish_mmc_get_ro,
|
|
+};
|
|
+
|
|
+static int __init goldfish_mmc_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct mmc_host *mmc;
|
|
+ struct goldfish_mmc_host *host = NULL;
|
|
+ struct resource *res;
|
|
+ int ret = 0;
|
|
+ int irq;
|
|
+ dma_addr_t buf_addr;
|
|
+
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ irq = platform_get_irq(pdev, 0);
|
|
+ if (res == NULL || irq < 0)
|
|
+ return -ENXIO;
|
|
+
|
|
+ mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
|
|
+ if (mmc == NULL) {
|
|
+ ret = -ENOMEM;
|
|
+ goto err_alloc_host_failed;
|
|
+ }
|
|
+
|
|
+ host = mmc_priv(mmc);
|
|
+ host->mmc = mmc;
|
|
+ host->reg_base = IO_ADDRESS(res->start - IO_START);
|
|
+ host->virt_base = dma_alloc_writecombine(&pdev->dev, BUFFER_SIZE,
|
|
+ &buf_addr, GFP_KERNEL);
|
|
+ if(host->virt_base == 0) {
|
|
+ ret = -EBUSY;
|
|
+ goto dma_alloc_failed;
|
|
+ }
|
|
+ host->phys_base = buf_addr;
|
|
+
|
|
+ host->id = pdev->id;
|
|
+ host->irq = irq;
|
|
+
|
|
+ mmc->ops = &goldfish_mmc_ops;
|
|
+ mmc->f_min = 400000;
|
|
+ mmc->f_max = 24000000;
|
|
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
+ mmc->caps = MMC_CAP_4_BIT_DATA;
|
|
+
|
|
+ /* Use scatterlist DMA to reduce per-transfer costs.
|
|
+ * NOTE max_seg_size assumption that small blocks aren't
|
|
+ * normally used (except e.g. for reading SD registers).
|
|
+ */
|
|
+ mmc->max_phys_segs = 32;
|
|
+ mmc->max_hw_segs = 32;
|
|
+ mmc->max_blk_size = 2048; /* MMC_BLOCK_LENGTH is 11 bits (+1) */
|
|
+ mmc->max_blk_count = 2048; /* MMC_BLOCK_COUNT is 11 bits (+1) */
|
|
+ mmc->max_req_size = BUFFER_SIZE;
|
|
+ mmc->max_seg_size = mmc->max_req_size;
|
|
+
|
|
+ ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
|
|
+ if (ret)
|
|
+ goto err_request_irq_failed;
|
|
+
|
|
+ host->dev = &pdev->dev;
|
|
+ platform_set_drvdata(pdev, host);
|
|
+
|
|
+ ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
|
|
+ if (ret)
|
|
+ dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
|
|
+
|
|
+ mmc_add_host(mmc);
|
|
+
|
|
+ GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
|
|
+ GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
|
|
+ MMC_STAT_END_OF_CMD | MMC_STAT_END_OF_DATA | MMC_STAT_STATE_CHANGE
|
|
+ );
|
|
+
|
|
+ // we start with the card present
|
|
+ kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
|
|
+ mmc_detect_change(host->mmc, 0);
|
|
+
|
|
+ INIT_WORK(&host->switch_work, goldfish_mmc_switch_handler);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err_request_irq_failed:
|
|
+ dma_free_writecombine(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
|
|
+dma_alloc_failed:
|
|
+ mmc_free_host(host->mmc);
|
|
+err_alloc_host_failed:
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int goldfish_mmc_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct goldfish_mmc_host *host = platform_get_drvdata(pdev);
|
|
+
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+
|
|
+ BUG_ON(host == NULL);
|
|
+
|
|
+ mmc_remove_host(host->mmc);
|
|
+ free_irq(host->irq, host);
|
|
+ dma_free_writecombine(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
|
|
+ mmc_free_host(host->mmc);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver goldfish_mmc_driver = {
|
|
+ .probe = goldfish_mmc_probe,
|
|
+ .remove = goldfish_mmc_remove,
|
|
+ .driver = {
|
|
+ .name = DRIVER_NAME,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init goldfish_mmc_init(void)
|
|
+{
|
|
+ return platform_driver_register(&goldfish_mmc_driver);
|
|
+}
|
|
+
|
|
+static void __exit goldfish_mmc_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&goldfish_mmc_driver);
|
|
+}
|
|
+
|
|
+module_init(goldfish_mmc_init);
|
|
+module_exit(goldfish_mmc_exit);
|
|
+
|