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140 lines
4.5 KiB
Diff
140 lines
4.5 KiB
Diff
From 87043a64dd5185dc076b3c3ab2e421b3a8c47798 Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Thu, 23 Apr 2015 10:35:43 +0200
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Subject: [PATCH 09/76] dt-bindings: ARM: Mediatek: Document devicetree
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bindings for clock/reset controllers
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This adds the binding documentation for the apmixedsys, perisys and
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infracfg controllers found on Mediatek SoCs.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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---
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.../bindings/arm/mediatek/mediatek,apmixedsys.txt | 23 +++++++++++++++
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.../bindings/arm/mediatek/mediatek,infracfg.txt | 30 ++++++++++++++++++++
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.../bindings/arm/mediatek/mediatek,pericfg.txt | 30 ++++++++++++++++++++
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.../bindings/arm/mediatek/mediatek,topckgen.txt | 23 +++++++++++++++
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4 files changed, 106 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
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@@ -0,0 +1,23 @@
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+Mediatek apmixedsys controller
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+==============================
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+
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+The Mediatek apmixedsys controller provides the PLLs to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be:
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+ - "mediatek,mt8135-apmixedsys"
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+ - "mediatek,mt8173-apmixedsys"
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+- #clock-cells: Must be 1
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+
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+The apmixedsys controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+
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+Example:
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+
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+apmixedsys: apmixedsys@10209000 {
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+ compatible = "mediatek,mt8173-apmixedsys";
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+ reg = <0 0x10209000 0 0x1000>;
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+ #clock-cells = <1>;
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+};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
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@@ -0,0 +1,30 @@
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+Mediatek infracfg controller
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+============================
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+
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+The Mediatek infracfg controller provides various clocks and reset
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+outputs to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be:
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+ - "mediatek,mt8135-infracfg", "syscon"
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+ - "mediatek,mt8173-infracfg", "syscon"
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+- #clock-cells: Must be 1
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+- #reset-cells: Must be 1
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+
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+The infracfg controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+Also it uses the common reset controller binding from
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+Documentation/devicetree/bindings/reset/reset.txt.
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+The available reset outputs are defined in
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+dt-bindings/reset-controller/mt*-resets.h
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+
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+Example:
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+
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+infracfg: infracfg@10001000 {
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+ compatible = "mediatek,mt8173-infracfg", "syscon";
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+ reg = <0 0x10001000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
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@@ -0,0 +1,30 @@
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+Mediatek pericfg controller
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+===========================
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+
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+The Mediatek pericfg controller provides various clocks and reset
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+outputs to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be:
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+ - "mediatek,mt8135-pericfg", "syscon"
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+ - "mediatek,mt8173-pericfg", "syscon"
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+- #clock-cells: Must be 1
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+- #reset-cells: Must be 1
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+
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+The pericfg controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+Also it uses the common reset controller binding from
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+Documentation/devicetree/bindings/reset/reset.txt.
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+The available reset outputs are defined in
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+dt-bindings/reset-controller/mt*-resets.h
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+
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+Example:
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+
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+pericfg: pericfg@10003000 {
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+ compatible = "mediatek,mt8173-pericfg", "syscon";
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+ reg = <0 0x10003000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
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@@ -0,0 +1,23 @@
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+Mediatek topckgen controller
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+============================
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+
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+The Mediatek topckgen controller provides various clocks to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be:
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+ - "mediatek,mt8135-topckgen"
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+ - "mediatek,mt8173-topckgen"
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+- #clock-cells: Must be 1
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+
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+The topckgen controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+
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+Example:
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+
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+topckgen: topckgen@10000000 {
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+ compatible = "mediatek,mt8173-topckgen";
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+ reg = <0 0x10000000 0 0x1000>;
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+ #clock-cells = <1>;
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+};
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