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48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
From 5ebee96094c5a97a89a986108242cca9d853ff55 Mon Sep 17 00:00:00 2001
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From: Roy Pledge <roy.pledge@nxp.com>
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Date: Wed, 27 Sep 2017 14:50:08 -0400
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Subject: [PATCH] staging/fsl_qbman: Calculate valid bit from MC-RR
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Use the management commmand response registers to determine
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the next expected valid bit when initializing a software
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portal. This avoids using the wrong valid bit in cases
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where a command was partially written but then not
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completed.
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Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
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---
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drivers/staging/fsl_qbman/qman_low.h | 19 +++++++++++++++++--
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1 file changed, 17 insertions(+), 2 deletions(-)
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--- a/drivers/staging/fsl_qbman/qman_low.h
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+++ b/drivers/staging/fsl_qbman/qman_low.h
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@@ -1095,11 +1095,26 @@ static inline void qm_mr_set_ithresh(str
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static inline int qm_mc_init(struct qm_portal *portal)
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{
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+ u8 rr0, rr1;
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register struct qm_mc *mc = &portal->mc;
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+
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mc->cr = portal->addr.addr_ce + QM_CL_CR;
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mc->rr = portal->addr.addr_ce + QM_CL_RR0;
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- mc->rridx = (__raw_readb(&mc->cr->__dont_write_directly__verb) &
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- QM_MCC_VERB_VBIT) ? 0 : 1;
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+
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+ /*
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+ * The expected valid bit polarity for the next CR command is 0
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+ * if RR1 contains a valid response, and is 1 if RR0 contains a
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+ * valid response. If both RR contain all 0, this indicates either
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+ * that no command has been executed since reset (in which case the
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+ * expected valid bit polarity is 1)
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+ */
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+ rr0 = __raw_readb(&mc->rr->verb);
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+ rr1 = __raw_readb(&(mc->rr+1)->verb);
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+ if ((rr0 == 0 && rr1 == 0) || rr0 != 0)
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+ mc->rridx = 1;
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+ else
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+ mc->rridx = 0;
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+
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mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
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#ifdef CONFIG_FSL_DPA_CHECKING
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mc->state = qman_mc_idle;
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