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34 lines
1.8 KiB
Diff
34 lines
1.8 KiB
Diff
From 120c8f221cb18f6630d5cb954484bac88288cced Mon Sep 17 00:00:00 2001
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From: Haiying Wang <Haiying.Wang@freescale.com>
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Date: Wed, 22 Apr 2015 13:07:25 -0400
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Subject: [PATCH] arm64: add ioremap for normal cacheable non-shareable memory
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
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Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
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---
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arch/arm64/include/asm/io.h | 1 +
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arch/arm64/include/asm/pgtable-prot.h | 1 +
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2 files changed, 2 insertions(+)
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--- a/arch/arm64/include/asm/io.h
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+++ b/arch/arm64/include/asm/io.h
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@@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_
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#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
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#define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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+#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
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/*
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* PCI configuration space mapping function.
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--- a/arch/arm64/include/asm/pgtable-prot.h
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+++ b/arch/arm64/include/asm/pgtable-prot.h
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@@ -37,6 +37,7 @@
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#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
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#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
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#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
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+#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
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#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
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