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142 lines
5.0 KiB
Diff
142 lines
5.0 KiB
Diff
From: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com>
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Date: Thu, 2 Jun 2016 19:54:42 +0530
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Subject: [PATCH] ath10k: fix CCK h/w rates for QCA99X0 and newer chipsets
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CCK hardware table mapping from QCA99X0 onwards got revised.
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The CCK hardware rate values are in a proper order wrt. to
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rate and preamble as below
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ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
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ATH10K_HW_RATE_REV2_CCK_LP_2M = 2,
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ATH10K_HW_RATE_REV2_CCK_LP_5_5M = 3,
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ATH10K_HW_RATE_REV2_CCK_LP_11M = 4,
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ATH10K_HW_RATE_REV2_CCK_SP_2M = 5,
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ATH10K_HW_RATE_REV2_CCK_SP_5_5M = 6,
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ATH10K_HW_RATE_REV2_CCK_SP_11M = 7,
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This results in reporting of rx frames (with CCK rates)
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totally wrong for QCA99X0, QCA4019. Fix this by having
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separate CCK rate table for these chipsets with rev2 suffix
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and registering the correct rate mapping to mac80211 based on
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the new hw_param (introduced) 'cck_rate_map_rev2' which shall
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be true for any newchipsets from QCA99X0 onwards
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Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com>
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---
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--- a/drivers/net/wireless/ath/ath10k/core.c
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+++ b/drivers/net/wireless/ath/ath10k/core.c
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@@ -148,6 +148,8 @@ static const struct ath10k_hw_params ath
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.uart_pin = 7,
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.otp_exe_param = 0x00000700,
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.continuous_frag_desc = true,
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+ .cck_rate_map_rev2 = true,
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+ .cck_rate_map_rev2 = true,
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.channel_counters_freq_hz = 150000,
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.max_probe_resp_desc_thres = 24,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
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@@ -205,6 +207,7 @@ static const struct ath10k_hw_params ath
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.has_shifted_cc_wraparound = true,
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.otp_exe_param = 0x0010000,
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.continuous_frag_desc = true,
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+ .cck_rate_map_rev2 = true,
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.channel_counters_freq_hz = 125000,
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.max_probe_resp_desc_thres = 24,
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.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
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--- a/drivers/net/wireless/ath/ath10k/core.h
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+++ b/drivers/net/wireless/ath/ath10k/core.h
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@@ -716,6 +716,12 @@ struct ath10k {
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*/
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bool continuous_frag_desc;
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+ /* CCK hardware rate table mapping for the newer chipsets
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+ * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
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+ * are in a proper order with respect to the rate/preamble
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+ */
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+ bool cck_rate_map_rev2;
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+
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u32 channel_counters_freq_hz;
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/* Mgmt tx descriptors threshold for limiting probe response
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--- a/drivers/net/wireless/ath/ath10k/hw.h
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+++ b/drivers/net/wireless/ath/ath10k/hw.h
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@@ -315,6 +315,16 @@ enum ath10k_hw_rate_cck {
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ATH10K_HW_RATE_CCK_SP_2M,
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};
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+enum ath10k_hw_rate_rev2_cck {
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+ ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
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+ ATH10K_HW_RATE_REV2_CCK_LP_2M,
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+ ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
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+ ATH10K_HW_RATE_REV2_CCK_LP_11M,
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+ ATH10K_HW_RATE_REV2_CCK_SP_2M,
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+ ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
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+ ATH10K_HW_RATE_REV2_CCK_SP_11M,
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+};
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+
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enum ath10k_hw_4addr_pad {
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ATH10K_HW_4ADDR_PAD_AFTER,
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ATH10K_HW_4ADDR_PAD_BEFORE,
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--- a/drivers/net/wireless/ath/ath10k/mac.c
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+++ b/drivers/net/wireless/ath/ath10k/mac.c
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@@ -62,6 +62,32 @@ static struct ieee80211_rate ath10k_rate
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{ .bitrate = 540, .hw_value = ATH10K_HW_RATE_OFDM_54M },
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};
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+static struct ieee80211_rate ath10k_rates_rev2[] = {
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+ { .bitrate = 10,
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+ .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_1M },
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+ { .bitrate = 20,
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+ .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_2M,
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+ .hw_value_short = ATH10K_HW_RATE_REV2_CCK_SP_2M,
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+ .flags = IEEE80211_RATE_SHORT_PREAMBLE },
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+ { .bitrate = 55,
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+ .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
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+ .hw_value_short = ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
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+ .flags = IEEE80211_RATE_SHORT_PREAMBLE },
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+ { .bitrate = 110,
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+ .hw_value = ATH10K_HW_RATE_REV2_CCK_LP_11M,
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+ .hw_value_short = ATH10K_HW_RATE_REV2_CCK_SP_11M,
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+ .flags = IEEE80211_RATE_SHORT_PREAMBLE },
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+
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+ { .bitrate = 60, .hw_value = ATH10K_HW_RATE_OFDM_6M },
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+ { .bitrate = 90, .hw_value = ATH10K_HW_RATE_OFDM_9M },
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+ { .bitrate = 120, .hw_value = ATH10K_HW_RATE_OFDM_12M },
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+ { .bitrate = 180, .hw_value = ATH10K_HW_RATE_OFDM_18M },
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+ { .bitrate = 240, .hw_value = ATH10K_HW_RATE_OFDM_24M },
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+ { .bitrate = 360, .hw_value = ATH10K_HW_RATE_OFDM_36M },
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+ { .bitrate = 480, .hw_value = ATH10K_HW_RATE_OFDM_48M },
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+ { .bitrate = 540, .hw_value = ATH10K_HW_RATE_OFDM_54M },
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+};
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+
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#define ATH10K_MAC_FIRST_OFDM_RATE_IDX 4
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#define ath10k_a_rates (ath10k_rates + ATH10K_MAC_FIRST_OFDM_RATE_IDX)
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@@ -70,6 +96,9 @@ static struct ieee80211_rate ath10k_rate
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#define ath10k_g_rates (ath10k_rates + 0)
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#define ath10k_g_rates_size (ARRAY_SIZE(ath10k_rates))
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+#define ath10k_g_rates_rev2 (ath10k_rates_rev2 + 0)
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+#define ath10k_g_rates_rev2_size (ARRAY_SIZE(ath10k_rates_rev2))
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+
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static bool ath10k_mac_bitrate_is_cck(int bitrate)
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{
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switch (bitrate) {
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@@ -7720,8 +7749,14 @@ int ath10k_mac_register(struct ath10k *a
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band = &ar->mac.sbands[NL80211_BAND_2GHZ];
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band->n_channels = ARRAY_SIZE(ath10k_2ghz_channels);
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band->channels = channels;
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- band->n_bitrates = ath10k_g_rates_size;
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- band->bitrates = ath10k_g_rates;
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+
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+ if (ar->hw_params.cck_rate_map_rev2) {
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+ band->n_bitrates = ath10k_g_rates_rev2_size;
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+ band->bitrates = ath10k_g_rates_rev2;
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+ } else {
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+ band->n_bitrates = ath10k_g_rates_size;
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+ band->bitrates = ath10k_g_rates;
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+ }
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ar->hw->wiphy->bands[NL80211_BAND_2GHZ] = band;
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}
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