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392 lines
12 KiB
Diff
392 lines
12 KiB
Diff
From afe108e638a2dd441b11cd2c7b1e0658bb47b5e8 Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Tue, 26 Apr 2016 13:14:45 -0500
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Subject: [PATCH 10/69] spi: qup: call io_config in mode specific function
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DMA transactions should only only need to call io_config only once, but
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block mode might call it several times to setup several transactions so
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it can handle reads/writes larger than the max size per transaction, so
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we move the call to the do_ functions.
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This is just refactoring, there should be no functional change
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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---
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drivers/spi/spi-qup.c | 327 +++++++++++++++++++++++++-------------------------
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1 file changed, 166 insertions(+), 161 deletions(-)
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--- a/drivers/spi/spi-qup.c
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+++ b/drivers/spi/spi-qup.c
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@@ -418,13 +418,170 @@ static void spi_qup_dma_terminate(struct
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dmaengine_terminate_all(master->dma_rx);
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}
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-static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer,
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+/* prep qup for another spi transaction of specific type */
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+static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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+{
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+ struct spi_qup *controller = spi_master_get_devdata(spi->master);
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+ u32 config, iomode, control;
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+ unsigned long flags;
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+
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+ reinit_completion(&controller->done);
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+ reinit_completion(&controller->dma_tx_done);
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+
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+ spin_lock_irqsave(&controller->lock, flags);
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+ controller->xfer = xfer;
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+ controller->error = 0;
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+ controller->rx_bytes = 0;
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+ controller->tx_bytes = 0;
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+ spin_unlock_irqrestore(&controller->lock, flags);
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+
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+ if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
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+ dev_err(controller->dev, "cannot set RESET state\n");
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+ return -EIO;
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+ }
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+
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+ switch (controller->mode) {
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+ case QUP_IO_M_MODE_FIFO:
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_READ_CNT);
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_WRITE_CNT);
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+ /* must be zero for FIFO */
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+ writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
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+ writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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+ break;
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+ case QUP_IO_M_MODE_BAM:
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_INPUT_CNT);
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_OUTPUT_CNT);
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+ /* must be zero for BLOCK and BAM */
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+ writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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+ writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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+ if (!controller->qup_v1) {
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+ void __iomem *input_cnt;
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+
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+ input_cnt = controller->base + QUP_MX_INPUT_CNT;
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+ /*
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+ * for DMA transfers, both QUP_MX_INPUT_CNT and
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+ * QUP_MX_OUTPUT_CNT must be zero to all cases
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+ * but one. That case is a non-balanced
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+ * transfer when there is only a rx_buf.
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+ */
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+ if (xfer->tx_buf)
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+ writel_relaxed(0, input_cnt);
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+ else
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+ writel_relaxed(controller->n_words,
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+ input_cnt);
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+
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+ writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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+ }
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+ break;
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+ case QUP_IO_M_MODE_BLOCK:
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_INPUT_CNT);
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_OUTPUT_CNT);
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+ /* must be zero for BLOCK and BAM */
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+ writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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+ writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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+ break;
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+ default:
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+ dev_err(controller->dev, "unknown mode = %d\n",
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+ controller->mode);
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+ return -EIO;
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+ }
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+
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+ iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
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+ /* Set input and output transfer mode */
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+ iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
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+
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+ if (!spi_qup_is_dma_xfer(controller->mode))
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+ iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
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+ else
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+ iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
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+
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+ iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
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+ iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
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+
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+ writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
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+
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+ control = readl_relaxed(controller->base + SPI_IO_CONTROL);
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+
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+ if (spi->mode & SPI_CPOL)
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+ control |= SPI_IO_C_CLK_IDLE_HIGH;
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+ else
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+ control &= ~SPI_IO_C_CLK_IDLE_HIGH;
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+
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+ writel_relaxed(control, controller->base + SPI_IO_CONTROL);
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+
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+ config = readl_relaxed(controller->base + SPI_CONFIG);
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+
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+ if (spi->mode & SPI_LOOP)
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+ config |= SPI_CONFIG_LOOPBACK;
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+ else
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+ config &= ~SPI_CONFIG_LOOPBACK;
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+
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+ if (spi->mode & SPI_CPHA)
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+ config &= ~SPI_CONFIG_INPUT_FIRST;
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+ else
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+ config |= SPI_CONFIG_INPUT_FIRST;
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+
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+ /*
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+ * HS_MODE improves signal stability for spi-clk high rates,
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+ * but is invalid in loop back mode.
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+ */
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+ if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
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+ config |= SPI_CONFIG_HS_MODE;
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+ else
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+ config &= ~SPI_CONFIG_HS_MODE;
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+
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+ writel_relaxed(config, controller->base + SPI_CONFIG);
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+
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+ config = readl_relaxed(controller->base + QUP_CONFIG);
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+ config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
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+ config |= xfer->bits_per_word - 1;
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+ config |= QUP_CONFIG_SPI_MODE;
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+
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+ if (spi_qup_is_dma_xfer(controller->mode)) {
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+ if (!xfer->tx_buf)
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+ config |= QUP_CONFIG_NO_OUTPUT;
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+ if (!xfer->rx_buf)
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+ config |= QUP_CONFIG_NO_INPUT;
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+ }
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+
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+ writel_relaxed(config, controller->base + QUP_CONFIG);
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+
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+ /* only write to OPERATIONAL_MASK when register is present */
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+ if (!controller->qup_v1) {
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+ u32 mask = 0;
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+
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+ /*
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+ * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
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+ * status change in BAM mode
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+ */
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+
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+ if (spi_qup_is_dma_xfer(controller->mode))
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+ mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
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+
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+ writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
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+ }
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+
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+ return 0;
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+}
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+
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+static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
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unsigned long timeout)
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{
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+ struct spi_master *master = spi->master;
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struct spi_qup *qup = spi_master_get_devdata(master);
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dma_async_tx_callback rx_done = NULL, tx_done = NULL;
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int ret;
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+ ret = spi_qup_io_config(spi, xfer);
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+ if (ret)
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+ return ret;
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+
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/* before issuing the descriptors, set the QUP to run */
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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@@ -467,12 +624,17 @@ unsigned long timeout)
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return ret;
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}
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-static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer,
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+static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
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unsigned long timeout)
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{
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+ struct spi_master *master = spi->master;
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struct spi_qup *qup = spi_master_get_devdata(master);
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int ret;
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+ ret = spi_qup_io_config(spi, xfer);
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+ if (ret)
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+ return ret;
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+
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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dev_warn(qup->dev, "cannot set RUN state\n");
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@@ -619,159 +781,6 @@ static int spi_qup_io_prep(struct spi_de
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return 0;
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}
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-/* prep qup for another spi transaction of specific type */
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-static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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-{
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- struct spi_qup *controller = spi_master_get_devdata(spi->master);
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- u32 config, iomode, control;
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- unsigned long flags;
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-
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- reinit_completion(&controller->done);
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- reinit_completion(&controller->dma_tx_done);
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-
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- spin_lock_irqsave(&controller->lock, flags);
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- controller->xfer = xfer;
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- controller->error = 0;
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- controller->rx_bytes = 0;
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- controller->tx_bytes = 0;
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- spin_unlock_irqrestore(&controller->lock, flags);
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-
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-
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- if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
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- dev_err(controller->dev, "cannot set RESET state\n");
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- return -EIO;
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- }
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-
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- switch (controller->mode) {
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- case QUP_IO_M_MODE_FIFO:
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- writel_relaxed(controller->n_words,
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- controller->base + QUP_MX_READ_CNT);
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- writel_relaxed(controller->n_words,
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- controller->base + QUP_MX_WRITE_CNT);
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- /* must be zero for FIFO */
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- writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
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- writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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- break;
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- case QUP_IO_M_MODE_BAM:
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- writel_relaxed(controller->n_words,
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- controller->base + QUP_MX_INPUT_CNT);
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- writel_relaxed(controller->n_words,
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- controller->base + QUP_MX_OUTPUT_CNT);
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- /* must be zero for BLOCK and BAM */
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- writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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- writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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- if (!controller->qup_v1) {
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- void __iomem *input_cnt;
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-
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- input_cnt = controller->base + QUP_MX_INPUT_CNT;
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- /*
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- * for DMA transfers, both QUP_MX_INPUT_CNT and
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- * QUP_MX_OUTPUT_CNT must be zero to all cases
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- * but one. That case is a non-balanced
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- * transfer when there is only a rx_buf.
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- */
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- if (xfer->tx_buf)
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- writel_relaxed(0, input_cnt);
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- else
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- writel_relaxed(controller->n_words,
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- input_cnt);
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-
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- writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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- }
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- break;
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- case QUP_IO_M_MODE_BLOCK:
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- writel_relaxed(controller->n_words,
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- controller->base + QUP_MX_INPUT_CNT);
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- writel_relaxed(controller->n_words,
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- controller->base + QUP_MX_OUTPUT_CNT);
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- /* must be zero for BLOCK and BAM */
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- writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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- writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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- break;
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- default:
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- dev_err(controller->dev, "unknown mode = %d\n",
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- controller->mode);
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- return -EIO;
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- }
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-
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- iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
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- /* Set input and output transfer mode */
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- iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
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-
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- if (!spi_qup_is_dma_xfer(controller->mode))
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- iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
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- else
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- iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
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-
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- iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
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- iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
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-
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- writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
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-
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- control = readl_relaxed(controller->base + SPI_IO_CONTROL);
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-
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- if (spi->mode & SPI_CPOL)
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- control |= SPI_IO_C_CLK_IDLE_HIGH;
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- else
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- control &= ~SPI_IO_C_CLK_IDLE_HIGH;
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-
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- writel_relaxed(control, controller->base + SPI_IO_CONTROL);
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-
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- config = readl_relaxed(controller->base + SPI_CONFIG);
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-
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- if (spi->mode & SPI_LOOP)
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- config |= SPI_CONFIG_LOOPBACK;
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- else
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- config &= ~SPI_CONFIG_LOOPBACK;
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-
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- if (spi->mode & SPI_CPHA)
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- config &= ~SPI_CONFIG_INPUT_FIRST;
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- else
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- config |= SPI_CONFIG_INPUT_FIRST;
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-
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- /*
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- * HS_MODE improves signal stability for spi-clk high rates,
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- * but is invalid in loop back mode.
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- */
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- if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
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- config |= SPI_CONFIG_HS_MODE;
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- else
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- config &= ~SPI_CONFIG_HS_MODE;
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-
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- writel_relaxed(config, controller->base + SPI_CONFIG);
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-
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- config = readl_relaxed(controller->base + QUP_CONFIG);
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- config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
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- config |= xfer->bits_per_word - 1;
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- config |= QUP_CONFIG_SPI_MODE;
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-
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- if (spi_qup_is_dma_xfer(controller->mode)) {
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- if (!xfer->tx_buf)
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- config |= QUP_CONFIG_NO_OUTPUT;
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- if (!xfer->rx_buf)
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- config |= QUP_CONFIG_NO_INPUT;
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- }
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-
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- writel_relaxed(config, controller->base + QUP_CONFIG);
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-
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- /* only write to OPERATIONAL_MASK when register is present */
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- if (!controller->qup_v1) {
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- u32 mask = 0;
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-
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- /*
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- * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
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- * status change in BAM mode
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- */
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-
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- if (spi_qup_is_dma_xfer(controller->mode))
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- mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
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-
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- writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
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- }
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-
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- return 0;
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-}
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-
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static int spi_qup_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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@@ -784,18 +793,14 @@ static int spi_qup_transfer_one(struct s
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if (ret)
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return ret;
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- ret = spi_qup_io_config(spi, xfer);
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- if (ret)
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- return ret;
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-
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timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
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timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
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timeout = 100 * msecs_to_jiffies(timeout);
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if (spi_qup_is_dma_xfer(controller->mode))
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- ret = spi_qup_do_dma(master, xfer, timeout);
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+ ret = spi_qup_do_dma(spi, xfer, timeout);
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else
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- ret = spi_qup_do_pio(master, xfer, timeout);
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+ ret = spi_qup_do_pio(spi, xfer, timeout);
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if (ret)
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goto exit;
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