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541 lines
14 KiB
C
541 lines
14 KiB
C
/* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2018 John Crispin <john@phrozen.org>
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*/
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#include "mtk_offload.h"
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#define INVALID 0
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#define UNBIND 1
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#define BIND 2
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#define FIN 3
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#define IPV4_HNAPT 0
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#define IPV4_HNAT 1
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static u32
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mtk_flow_hash_v4(struct flow_offload_tuple *tuple)
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{
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u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port);
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u32 src = ntohl(tuple->dst_v4.s_addr);
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u32 dst = ntohl(tuple->src_v4.s_addr);
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u32 hash = (ports & src) | ((~ports) & dst);
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u32 hash_23_0 = hash & 0xffffff;
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u32 hash_31_24 = hash & 0xff000000;
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hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24));
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hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff);
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hash &= 0x7ff;
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hash *= 2;;
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return hash;
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}
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static int
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mtk_foe_prepare_v4(struct mtk_foe_entry *entry,
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struct flow_offload_tuple *tuple,
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struct flow_offload_tuple *dest_tuple,
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struct flow_offload_hw_path *src,
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struct flow_offload_hw_path *dest)
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{
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int is_mcast = !!is_multicast_ether_addr(dest->eth_dest);
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if (tuple->l4proto == IPPROTO_UDP)
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entry->ipv4_hnapt.bfib1.udp = 1;
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entry->ipv4_hnapt.etype = htons(ETH_P_IP);
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entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT;
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entry->ipv4_hnapt.iblk2.fqos = 0;
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entry->ipv4_hnapt.bfib1.ttl = 1;
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entry->ipv4_hnapt.bfib1.cah = 1;
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entry->ipv4_hnapt.bfib1.ka = 1;
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entry->ipv4_hnapt.iblk2.mcast = is_mcast;
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entry->ipv4_hnapt.iblk2.dscp = 0;
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entry->ipv4_hnapt.iblk2.port_mg = 0x3f;
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entry->ipv4_hnapt.iblk2.port_ag = 0x1f;
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#ifdef CONFIG_NET_RALINK_HW_QOS
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entry->ipv4_hnapt.iblk2.qid = 1;
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entry->ipv4_hnapt.iblk2.fqos = 1;
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#endif
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#ifdef CONFIG_RALINK
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entry->ipv4_hnapt.iblk2.dp = 1;
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if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1))
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entry->ipv4_hnapt.iblk2.qid += 8;
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#else
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entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1;
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#endif
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entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr);
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entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr);
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entry->ipv4_hnapt.sport = ntohs(tuple->src_port);
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entry->ipv4_hnapt.dport = ntohs(tuple->dst_port);
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entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr);
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entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr);
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entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port);
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entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port);
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entry->bfib1.state = BIND;
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if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) {
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entry->bfib1.psn = 1;
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entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES);
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entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid;
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}
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if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
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entry->ipv4_hnapt.vlan1 = dest->vlan_id;
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entry->bfib1.vlan_layer = 1;
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switch (dest->vlan_proto) {
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case htons(ETH_P_8021Q):
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entry->ipv4_hnapt.bfib1.vpm = 1;
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break;
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case htons(ETH_P_8021AD):
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entry->ipv4_hnapt.bfib1.vpm = 2;
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break;
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default:
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return -EINVAL;
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}
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}
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return 0;
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}
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static void
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mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac)
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{
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entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac));
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entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4]));
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entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac));
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entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4]));
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}
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static int
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mtk_check_entry_available(struct mtk_eth *eth, u32 hash)
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{
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struct mtk_foe_entry entry = ((struct mtk_foe_entry *)eth->foe_table)[hash];
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return (entry.bfib1.state == BIND)? 0:1;
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}
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static void
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mtk_foe_write(struct mtk_eth *eth, u32 hash,
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struct mtk_foe_entry *entry)
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{
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struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table;
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memcpy(&table[hash], entry, sizeof(*entry));
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}
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int mtk_flow_offload(struct mtk_eth *eth,
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enum flow_offload_type type,
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struct flow_offload *flow,
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struct flow_offload_hw_path *src,
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struct flow_offload_hw_path *dest)
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{
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struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple;
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struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple;
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u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff);
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u32 ohash, rhash;
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struct mtk_foe_entry orig = {
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.bfib1.time_stamp = time_stamp,
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.bfib1.psn = 0,
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};
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struct mtk_foe_entry reply = {
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.bfib1.time_stamp = time_stamp,
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.bfib1.psn = 0,
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};
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if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP)
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return -EINVAL;
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if (type == FLOW_OFFLOAD_DEL) {
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flow = NULL;
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synchronize_rcu();
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return 0;
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}
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switch (otuple->l3proto) {
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case AF_INET:
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if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) ||
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mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src))
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return -EINVAL;
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ohash = mtk_flow_hash_v4(otuple);
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rhash = mtk_flow_hash_v4(rtuple);
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break;
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case AF_INET6:
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return -EINVAL;
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default:
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return -EINVAL;
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}
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/* Two-way hash: when hash collision occurs, the hash value will be shifted to the next position. */
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if (!mtk_check_entry_available(eth, ohash)){
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if (!mtk_check_entry_available(eth, ohash + 1))
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return -EINVAL;
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ohash += 1;
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}
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if (!mtk_check_entry_available(eth, rhash)){
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if (!mtk_check_entry_available(eth, rhash + 1))
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return -EINVAL;
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rhash += 1;
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}
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mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest);
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mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest);
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mtk_foe_write(eth, ohash, &orig);
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mtk_foe_write(eth, rhash, &reply);
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rcu_assign_pointer(eth->foe_flow_table[ohash], flow);
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rcu_assign_pointer(eth->foe_flow_table[rhash], flow);
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return 0;
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}
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#ifdef CONFIG_NET_RALINK_HW_QOS
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#define QDMA_TX_SCH_TX 0x1a14
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static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate)
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{
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int exp = 0, shift = 0;
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u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX);
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u32 val = 0;
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if (rate)
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val = BIT(11);
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while (rate > 127) {
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rate /= 10;
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exp++;
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}
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val |= (rate & 0x7f) << 4;
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val |= exp & 0xf;
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if (id)
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shift = 16;
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reg &= ~(0xffff << shift);
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reg |= val << shift;
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mtk_w32(eth, val, QDMA_TX_SCH_TX);
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}
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#define QTX_CFG(x) (0x1800 + (x * 0x10))
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#define QTX_SCH(x) (0x1804 + (x * 0x10))
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static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate)
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{
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int max_exp = 0, min_exp = 0;
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u32 reg;
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if (id >= 16)
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return;
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reg = mtk_r32(eth, QTX_SCH(id));
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reg &= 0x70000000;
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if (sched)
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reg |= BIT(31);
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if (min_rate)
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reg |= BIT(27);
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if (max_rate)
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reg |= BIT(11);
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while (max_rate > 127) {
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max_rate /= 10;
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max_exp++;
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}
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while (min_rate > 127) {
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min_rate /= 10;
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min_exp++;
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}
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reg |= (min_rate & 0x7f) << 20;
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reg |= (min_exp & 0xf) << 16;
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reg |= (weight & 0xf) << 12;
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reg |= (max_rate & 0x7f) << 4;
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reg |= max_exp & 0xf;
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mtk_w32(eth, reg, QTX_SCH(id));
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resv &= 0xff;
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reg = mtk_r32(eth, QTX_CFG(id));
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reg &= 0xffff0000;
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reg |= (resv << 8) | resv;
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mtk_w32(eth, reg, QTX_CFG(id));
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}
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#endif
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static int mtk_init_foe_table(struct mtk_eth *eth)
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{
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if (eth->foe_table)
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return 0;
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eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT,
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sizeof(*eth->foe_flow_table),
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GFP_KERNEL);
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if (!eth->foe_flow_table)
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return -EINVAL;
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/* map the FOE table */
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eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ,
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ð->foe_table_phys, GFP_KERNEL);
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if (!eth->foe_table) {
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dev_err(eth->dev, "failed to allocate foe table\n");
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kfree(eth->foe_flow_table);
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return -ENOMEM;
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}
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return 0;
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}
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static int mtk_ppe_start(struct mtk_eth *eth)
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{
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int ret;
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ret = mtk_init_foe_table(eth);
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if (ret)
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return ret;
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/* tell the PPE about the tables base address */
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mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE);
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/* flush the table */
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memset(eth->foe_table, 0, MTK_PPE_TBL_SZ);
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/* setup hashing */
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mtk_m32(eth,
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MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK,
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MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K,
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MTK_REG_PPE_TB_CFG);
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/* set the default hashing seed */
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mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED);
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/* each foe entry is 64bytes and is setup by cpu forwarding*/
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mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK |
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MTK_PPE_TB_CFG_SMA_MASK,
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MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU,
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MTK_REG_PPE_TB_CFG);
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/* set ip proto */
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mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK);
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/* setup caching */
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mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
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mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN,
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MTK_REG_PPE_CAH_CTRL);
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/* enable FOE */
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mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
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MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
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MTK_PPE_FLOW_CFG_IPV4_GREK_EN,
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MTK_REG_PPE_FLOW_CFG);
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/* setup flow entry un/bind aging */
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mtk_m32(eth, 0,
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MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE |
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MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
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MTK_PPE_TB_CFG_TCP_AGE,
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MTK_REG_PPE_TB_CFG);
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mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK,
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MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA,
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MTK_REG_PPE_UNB_AGE);
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mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK |
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MTK_PPE_BND_AGE0_UDP_DLTA_MASK,
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MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA,
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MTK_REG_PPE_BND_AGE0);
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mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK |
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MTK_PPE_BND_AGE1_TCP_DLTA_MASK,
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MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA,
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MTK_REG_PPE_BND_AGE1);
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/* setup flow entry keep alive */
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mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK, MTK_PPE_TB_CFG_KA,
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MTK_REG_PPE_TB_CFG);
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mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA);
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/* setup flow entry rate limit */
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mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0);
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mtk_w32(eth, MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1);
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mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 1, MTK_REG_PPE_BNDR);
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/* enable the PPE */
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mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG);
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#ifdef CONFIG_RALINK
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/* set the default forwarding port to QDMA */
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mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT);
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#else
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/* set the default forwarding port to QDMA */
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mtk_w32(eth, 0x55555555, MTK_REG_PPE_DFT_CPORT);
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#endif
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/* allow packets with TTL=0 */
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mtk_m32(eth, MTK_PPE_GLO_CFG_TTL0_DROP, 0, MTK_REG_PPE_GLO_CFG);
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/* send all traffic from gmac to the ppe */
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mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0));
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mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1));
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dev_info(eth->dev, "PPE started\n");
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#ifdef CONFIG_NET_RALINK_HW_QOS
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mtk_ppe_scheduler(eth, 0, 500000);
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mtk_ppe_scheduler(eth, 1, 500000);
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mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0);
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mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0);
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mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0);
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mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0);
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#endif
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return 0;
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}
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|
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static int mtk_ppe_busy_wait(struct mtk_eth *eth)
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{
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unsigned long t_start = jiffies;
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u32 r = 0;
|
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|
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while (1) {
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r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG);
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if (!(r & MTK_PPE_GLO_CFG_BUSY))
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return 0;
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if (time_after(jiffies, t_start + HZ))
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break;
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usleep_range(10, 20);
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}
|
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|
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dev_err(eth->dev, "ppe: table busy timeout - resetting\n");
|
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reset_control_reset(eth->rst_ppe);
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|
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return -ETIMEDOUT;
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}
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|
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static int mtk_ppe_stop(struct mtk_eth *eth)
|
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{
|
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u32 r1 = 0, r2 = 0;
|
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int i;
|
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|
|
/* discard all traffic while we disable the PPE */
|
|
mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0));
|
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mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1));
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|
|
if (mtk_ppe_busy_wait(eth))
|
|
return -ETIMEDOUT;
|
|
|
|
/* invalidate all flow table entries */
|
|
for (i = 0; i < MTK_PPE_ENTRY_CNT; i++)
|
|
eth->foe_table[i].bfib1.state = FOE_STATE_INVALID;
|
|
|
|
/* disable caching */
|
|
mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
|
|
mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0,
|
|
MTK_REG_PPE_CAH_CTRL);
|
|
|
|
/* flush cache has to be ahead of hnat diable --*/
|
|
mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG);
|
|
|
|
/* disable FOE */
|
|
mtk_m32(eth,
|
|
MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
|
|
MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
|
|
MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE,
|
|
0, MTK_REG_PPE_FLOW_CFG);
|
|
|
|
/* disable FOE aging */
|
|
mtk_m32(eth, 0,
|
|
MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
|
|
MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE |
|
|
MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG);
|
|
|
|
r1 = mtk_r32(eth, 0x100);
|
|
r2 = mtk_r32(eth, 0x10c);
|
|
|
|
dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2);
|
|
|
|
if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) ||
|
|
((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) {
|
|
dev_info(eth->dev, "reset pse\n");
|
|
mtk_w32(eth, 0x1, 0x4);
|
|
}
|
|
|
|
/* set the foe entry base address to 0 */
|
|
mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE);
|
|
|
|
if (mtk_ppe_busy_wait(eth))
|
|
return -ETIMEDOUT;
|
|
|
|
/* send all traffic back to the DMA engine */
|
|
#ifdef CONFIG_RALINK
|
|
mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0));
|
|
mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1));
|
|
#else
|
|
mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(0));
|
|
mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(1));
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static void mtk_offload_keepalive(struct fe_priv *eth, unsigned int hash)
|
|
{
|
|
struct flow_offload *flow;
|
|
|
|
rcu_read_lock();
|
|
flow = rcu_dereference(eth->foe_flow_table[hash]);
|
|
if (flow)
|
|
flow->timeout = jiffies + 30 * HZ;
|
|
rcu_read_unlock();
|
|
}
|
|
|
|
int mtk_offload_check_rx(struct fe_priv *eth, struct sk_buff *skb, u32 rxd4)
|
|
{
|
|
unsigned int hash;
|
|
|
|
switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) {
|
|
case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR:
|
|
case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR:
|
|
case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR:
|
|
hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4);
|
|
mtk_offload_keepalive(eth, hash);
|
|
return -1;
|
|
case MTK_CPU_REASON_PACKET_SAMPLING:
|
|
return -1;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int mtk_ppe_probe(struct mtk_eth *eth)
|
|
{
|
|
int err;
|
|
|
|
err = mtk_ppe_start(eth);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mtk_ppe_debugfs_init(eth);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mtk_ppe_remove(struct mtk_eth *eth)
|
|
{
|
|
mtk_ppe_stop(eth);
|
|
}
|