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255 lines
5.9 KiB
C
255 lines
5.9 KiB
C
/*
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* Atheros AR71xx built-in ethernet mac driver
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on Atheros' AG7100 driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/of_mdio.h>
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#include "ag71xx.h"
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#define AG71XX_MDIO_RETRY 1000
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#define AG71XX_MDIO_DELAY 5
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static int bus_count;
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static int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am)
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{
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int i;
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for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
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u32 busy;
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udelay(AG71XX_MDIO_DELAY);
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regmap_read(am->mii_regmap, AG71XX_REG_MII_IND, &busy);
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if (!busy)
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return 0;
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udelay(AG71XX_MDIO_DELAY);
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}
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pr_err("%s: MDIO operation timed out\n", am->mii_bus->name);
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return -ETIMEDOUT;
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}
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static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
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{
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struct ag71xx_mdio *am = bus->priv;
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int err;
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int ret;
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err = ag71xx_mdio_wait_busy(am);
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if (err)
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return 0xffff;
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regmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
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regmap_write(am->mii_regmap, AG71XX_REG_MII_ADDR,
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((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
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regmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_READ);
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err = ag71xx_mdio_wait_busy(am);
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if (err)
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return 0xffff;
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regmap_read(am->mii_regmap, AG71XX_REG_MII_STATUS, &ret);
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ret &= 0xffff;
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regmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
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DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
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return ret;
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}
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static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
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{
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struct ag71xx_mdio *am = bus->priv;
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DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
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regmap_write(am->mii_regmap, AG71XX_REG_MII_ADDR,
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((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
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regmap_write(am->mii_regmap, AG71XX_REG_MII_CTRL, val);
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ag71xx_mdio_wait_busy(am);
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return 0;
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}
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static const u32 ar71xx_mdio_div_table[] = {
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4, 4, 6, 8, 10, 14, 20, 28,
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};
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static const u32 ar7240_mdio_div_table[] = {
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2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
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};
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static const u32 ar933x_mdio_div_table[] = {
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4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
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};
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static int ag71xx_mdio_get_divider(struct device_node *np, u32 *div)
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{
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struct clk *ref_clk = of_clk_get(np, 0);
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unsigned long ref_clock;
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u32 mdio_clock;
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const u32 *table;
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int ndivs, i;
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if (IS_ERR(ref_clk))
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return -EINVAL;
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ref_clock = clk_get_rate(ref_clk);
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clk_put(ref_clk);
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if(of_property_read_u32(np, "qca,mdio-max-frequency", &mdio_clock)) {
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if (of_property_read_bool(np, "builtin-switch"))
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mdio_clock = 5000000;
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else
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mdio_clock = 2000000;
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}
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if (of_device_is_compatible(np, "qca,ar9330-mdio") ||
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of_device_is_compatible(np, "qca,ar9340-mdio")) {
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table = ar933x_mdio_div_table;
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ndivs = ARRAY_SIZE(ar933x_mdio_div_table);
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} else if (of_device_is_compatible(np, "qca,ar7240-mdio")) {
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table = ar7240_mdio_div_table;
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ndivs = ARRAY_SIZE(ar7240_mdio_div_table);
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} else {
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table = ar71xx_mdio_div_table;
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ndivs = ARRAY_SIZE(ar71xx_mdio_div_table);
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}
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for (i = 0; i < ndivs; i++) {
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unsigned long t;
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t = ref_clock / table[i];
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if (t <= mdio_clock) {
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*div = i;
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return 0;
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}
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}
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return -ENOENT;
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}
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static int ag71xx_mdio_reset(struct mii_bus *bus)
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{
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struct device_node *np = bus->dev.of_node;
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struct ag71xx_mdio *am = bus->priv;
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bool builtin_switch;
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u32 t;
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builtin_switch = of_property_read_bool(np, "builtin-switch");
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if (ag71xx_mdio_get_divider(np, &t)) {
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if (of_device_is_compatible(np, "qca,ar9340-mdio"))
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t = MII_CFG_CLK_DIV_58;
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else if (builtin_switch)
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t = MII_CFG_CLK_DIV_10;
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else
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t = MII_CFG_CLK_DIV_28;
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}
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regmap_write(am->mii_regmap, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
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udelay(100);
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regmap_write(am->mii_regmap, AG71XX_REG_MII_CFG, t);
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udelay(100);
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return 0;
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}
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static int ag71xx_mdio_probe(struct platform_device *pdev)
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{
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struct device *amdev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct ag71xx_mdio *am;
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struct mii_bus *mii_bus;
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bool builtin_switch;
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int i, err;
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am = devm_kzalloc(amdev, sizeof(*am), GFP_KERNEL);
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if (!am)
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return -ENOMEM;
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am->mii_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
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if (IS_ERR(am->mii_regmap))
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return PTR_ERR(am->mii_regmap);
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mii_bus = devm_mdiobus_alloc(amdev);
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if (!mii_bus)
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return -ENOMEM;
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am->mdio_reset = devm_reset_control_get_exclusive(amdev, "mdio");
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builtin_switch = of_property_read_bool(np, "builtin-switch");
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mii_bus->name = "ag71xx_mdio";
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mii_bus->read = ag71xx_mdio_mii_read;
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mii_bus->write = ag71xx_mdio_mii_write;
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mii_bus->reset = ag71xx_mdio_reset;
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mii_bus->priv = am;
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mii_bus->parent = amdev;
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snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, bus_count++);
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if (!builtin_switch &&
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of_property_read_u32(np, "phy-mask", &mii_bus->phy_mask))
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mii_bus->phy_mask = 0;
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for (i = 0; i < PHY_MAX_ADDR; i++)
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mii_bus->irq[i] = PHY_POLL;
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if (!IS_ERR(am->mdio_reset)) {
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reset_control_assert(am->mdio_reset);
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msleep(100);
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reset_control_deassert(am->mdio_reset);
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msleep(200);
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}
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err = of_mdiobus_register(mii_bus, np);
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if (err)
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return err;
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am->mii_bus = mii_bus;
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platform_set_drvdata(pdev, am);
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return 0;
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}
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static int ag71xx_mdio_remove(struct platform_device *pdev)
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{
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struct ag71xx_mdio *am = platform_get_drvdata(pdev);
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mdiobus_unregister(am->mii_bus);
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return 0;
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}
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static const struct of_device_id ag71xx_mdio_match[] = {
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{ .compatible = "qca,ar7240-mdio" },
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{ .compatible = "qca,ar9330-mdio" },
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{ .compatible = "qca,ar9340-mdio" },
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{ .compatible = "qca,ath79-mdio" },
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{}
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};
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static struct platform_driver ag71xx_mdio_driver = {
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.probe = ag71xx_mdio_probe,
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.remove = ag71xx_mdio_remove,
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.driver = {
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.name = "ag71xx-mdio",
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.of_match_table = ag71xx_mdio_match,
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}
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};
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module_platform_driver(ag71xx_mdio_driver);
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MODULE_LICENSE("GPL");
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