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290 lines
7.3 KiB
Diff
290 lines
7.3 KiB
Diff
diff -Nur linux-2.6.17/arch/mips/aruba/irq.c linux-2.6.17-openwrt/arch/mips/aruba/irq.c
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--- linux-2.6.17/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.17-openwrt/arch/mips/aruba/irq.c 2006-10-12 14:32:40.026285000 -0700
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@@ -0,0 +1,285 @@
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+#include <linux/errno.h>
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+#include <linux/init.h>
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+#include <linux/kernel_stat.h>
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+#include <linux/module.h>
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+#include <linux/signal.h>
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+#include <linux/sched.h>
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+#include <linux/types.h>
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+#include <linux/interrupt.h>
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+#include <linux/ioport.h>
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+#include <linux/timex.h>
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+#include <linux/slab.h>
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+#include <linux/random.h>
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+#include <linux/delay.h>
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+
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+#include <asm/bitops.h>
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+#include <asm/bootinfo.h>
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+#include <asm/io.h>
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+#include <asm/mipsregs.h>
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+#include <asm/system.h>
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+#include <asm/idt-boards/rc32434/rc32434.h>
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+#include <asm/idt-boards/rc32434/rc32434_gpio.h>
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+
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+#include <asm/irq.h>
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+
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+extern void aruba_timer_interrupt(struct pt_regs *regs);
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+
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+typedef struct {
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+ u32 mask;
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+ volatile u32 *base_addr;
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+} intr_group_t;
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+
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+static const intr_group_t intr_group_merlot[NUM_INTR_GROUPS] = {
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+ {0x00000000, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0)},
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+};
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+
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+#define READ_PEND_MERLOT(base) (*((volatile unsigned long *)(0xbc003010)))
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+#define READ_MASK_MERLOT(base) (*((volatile unsigned long *)(0xbc003014)))
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+#define WRITE_MASK_MERLOT(base, val) ((*((volatile unsigned long *)(0xbc003014))) = (val), READ_MASK_MERLOT())
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+
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+static const intr_group_t intr_group_muscat[NUM_INTR_GROUPS] = {
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+ {0x0000efff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
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+ {0x00001fff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
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+ {0x00000007, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
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+ {0x0003ffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
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+ {0xffffffff, (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
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+};
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+
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+#define READ_PEND_MUSCAT(base) (*(base))
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+#define READ_MASK_MUSCAT(base) (*(base + 2))
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+#define WRITE_MASK_MUSCAT(base, val) (*(base + 2) = (val))
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+
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+static inline int group_to_ip(unsigned int group)
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+{
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ return group + 2;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ return 6;
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+ }
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+}
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+
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+static inline void enable_local_irq(unsigned int irq)
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+{
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+ clear_c0_cause(0x100 << irq);
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+ set_c0_status(0x100 << irq);
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+ irq_enable_hazard();
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+}
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+
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+static inline void disable_local_irq(unsigned int irq)
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+{
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+ clear_c0_status(0x100 << irq);
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+ clear_c0_cause(0x100 << irq);
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+ irq_disable_hazard();
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+}
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+
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+static inline void aruba_irq_enable(unsigned int irq)
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+{
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+ unsigned long flags;
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+ unsigned int group, intr_bit;
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+ volatile unsigned int *addr;
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+
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+ local_irq_save(flags);
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+
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+ if (irq < GROUP0_IRQ_BASE) {
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+ enable_local_irq(irq);
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+ } else {
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+ int ip = irq - GROUP0_IRQ_BASE;
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ if (irq >= GROUP4_IRQ_BASE)
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+ idt_gpio->gpioistat &= ~(1 << (irq - GROUP4_IRQ_BASE));
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+
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+ // irqs are in groups of 32
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+ // ip is set to the remainder
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+ group = ip >> 5;
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+ ip &= 0x1f;
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+
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+ // bit -> 0 = unmask
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+ intr_bit = 1 << ip;
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+ addr = intr_group_muscat[group].base_addr;
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+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
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+ break;
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+
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ group = 0;
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+
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+ // bit -> 1 = unmasked
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+ intr_bit = 1 << ip;
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+ addr = intr_group_merlot[group].base_addr;
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+ WRITE_MASK_MERLOT(addr, READ_MASK_MERLOT(addr) | intr_bit);
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+ break;
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+ }
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+ enable_local_irq(group_to_ip(group));
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+ }
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+
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+ back_to_back_c0_hazard();
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+ local_irq_restore(flags);
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+}
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+
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+static void aruba_irq_disable(unsigned int irq)
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+{
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+ unsigned long flags;
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+ unsigned int group, intr_bit, mask;
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+ volatile unsigned int *addr;
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+
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+ local_irq_save(flags);
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+
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+ if (irq < GROUP0_IRQ_BASE) {
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+ disable_local_irq(irq);
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+ } else {
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+ int ip = irq - GROUP0_IRQ_BASE;
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ idt_gpio->gpioistat &= ~(1 << ip);
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+
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+ // irqs are in groups of 32
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+ // ip is set to the remainder
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+ group = ip >> 5;
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+ ip &= 0x1f;
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+
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+ // bit -> 1 = mask
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+ intr_bit = 1 << ip;
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+ addr = intr_group_muscat[group].base_addr;
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+
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+ mask = READ_MASK_MUSCAT(addr);
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+ mask |= intr_bit;
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+ WRITE_MASK_MUSCAT(addr, mask);
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+
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+ if (mask == intr_group_muscat[group].mask) {
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+ disable_local_irq(group_to_ip(group));
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+ }
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+ break;
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+
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ group = 0;
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+
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+ // bit -> 0 = masked
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+ intr_bit = 1 << ip;
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+ addr = intr_group_merlot[group].base_addr;
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+
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+ mask = READ_MASK_MERLOT(addr);
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+ mask &= ~intr_bit;
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+ WRITE_MASK_MERLOT(addr, mask);
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+
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+ if (mask == intr_group_merlot[group].mask) {
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+ disable_local_irq(group_to_ip(group));
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+ }
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+ break;
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+ }
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+ }
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+
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+ back_to_back_c0_hazard();
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+ local_irq_restore(flags);
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+}
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+
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+static unsigned int aruba_irq_startup(unsigned int irq)
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+{
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+ aruba_irq_enable(irq);
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+ return 0;
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+}
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+
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+#define aruba_irq_shutdown aruba_irq_disable
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+
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+static void aruba_irq_ack(unsigned int irq)
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+{
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+ aruba_irq_disable(irq);
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+}
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+
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+static void aruba_irq_end(unsigned int irq)
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+{
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+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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+ aruba_irq_enable(irq);
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+}
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+
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+static struct hw_interrupt_type aruba_irq_type = {
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+ .typename = "ARUBA",
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+ .startup = aruba_irq_startup,
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+ .shutdown = aruba_irq_shutdown,
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+ .enable = aruba_irq_enable,
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+ .disable = aruba_irq_disable,
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+ .ack = aruba_irq_ack,
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+ .end = aruba_irq_end,
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+};
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+
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+void __init arch_init_irq(void)
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+{
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+ int i;
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+ printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
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+ memset(irq_desc, 0, sizeof(irq_desc));
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+
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+ for (i = 0; i < RC32434_NR_IRQS; i++) {
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+ irq_desc[i].status = IRQ_DISABLED;
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+ irq_desc[i].action = NULL;
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+ irq_desc[i].depth = 1;
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+ irq_desc[i].handler = &aruba_irq_type;
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+ spin_lock_init(&irq_desc[i].lock);
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+ }
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+}
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+
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+/* Main Interrupt dispatcher */
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+
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+void plat_irq_dispatch(struct pt_regs *regs)
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+{
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+ unsigned int pend, group, ip;
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+ volatile unsigned int *addr;
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+ unsigned long cp0_cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
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+
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+ if (cp0_cause & CAUSEF_IP7)
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+ return aruba_timer_interrupt(regs);
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+
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+ if(cp0_cause == 0) {
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+ printk("INTERRUPT(S) FIRED WHILE MASKED\n");
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+#ifdef ARUBA_DEBUG
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+ // debuging use -- figure out which interrupt(s) fired
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+ cp0_cause = read_c0_cause() & CAUSEF_IP;
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+ while (cp0_cause) {
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+ unsigned long intr_bit;
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+ unsigned int irq_nr;
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+ intr_bit = (31 - rc32434_clz(cp0_cause));
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+ irq_nr = intr_bit - GROUP0_IRQ_BASE;
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+ printk(" ---> MASKED IRQ %d\n",irq_nr);
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+ cp0_cause &= ~(1 << intr_bit);
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+ }
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+#endif
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+ return;
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+ }
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ if ((ip = (cp0_cause & 0x7c00))) {
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+ group = 21 - rc32434_clz(ip);
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+
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+ addr = intr_group_muscat[group].base_addr;
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+
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+ pend = READ_PEND_MUSCAT(addr);
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+ pend &= ~READ_MASK_MUSCAT(addr); // only unmasked interrupts
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+ pend = 39 - rc32434_clz(pend);
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+ do_IRQ(pend + (group << 5), regs);
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+ }
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+ break;
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ if (cp0_cause & 0x4000) { // 1 << (8 +6) == irq 6
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+ // Misc Interrupt
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+ group = 0;
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+
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+ addr = intr_group_merlot[group].base_addr;
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+
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+ pend = READ_PEND_MERLOT(addr);
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+ pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
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+ pend = 31 - rc32434_clz(pend);
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+ do_IRQ(pend + GROUP0_IRQ_BASE, regs);
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+ }
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+ if ((ip = (cp0_cause & 0x3c00))) { // irq 2-5
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+ pend = 31 - rc32434_clz(ip);
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+ do_IRQ(pend - GROUP0_IRQ_BASE, regs);
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+ }
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+ break;
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+ }
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+}
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