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112 lines
3.6 KiB
Diff
112 lines
3.6 KiB
Diff
From 6e3022aeb5d221af838ad43a2163374aecacf929 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Thu, 14 Nov 2013 18:25:36 -0300
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Subject: [PATCH 150/203] mtd: nand: pxa3xx: Add a read/write buffers markers
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In preparation to support multiple (aka chunked, aka splitted)
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page I/O, this commit adds 'data_buff_pos' and 'oob_buff_pos' fields
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to keep track of where the next read (or write) should be done.
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This will allow multiple calls to handle_data_pio() to continue
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the read (or write) operation.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 40 +++++++++++++++++++++++++++++-----------
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1 file changed, 29 insertions(+), 11 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -176,6 +176,8 @@ struct pxa3xx_nand_info {
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unsigned int buf_start;
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unsigned int buf_count;
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unsigned int buf_size;
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+ unsigned int data_buff_pos;
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+ unsigned int oob_buff_pos;
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/* DMA information */
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int drcmr_dat;
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@@ -338,11 +340,12 @@ static void pxa3xx_nand_set_timing(struc
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* spare and ECC configuration.
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* Only applicable to READ0, READOOB and PAGEPROG commands.
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*/
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-static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
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+static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info,
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+ struct mtd_info *mtd)
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{
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int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
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- info->data_size = info->fifo_size;
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+ info->data_size = mtd->writesize;
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if (!oob_enable)
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return;
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@@ -430,26 +433,39 @@ static void disable_int(struct pxa3xx_na
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static void handle_data_pio(struct pxa3xx_nand_info *info)
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{
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+ unsigned int do_bytes = min(info->data_size, info->fifo_size);
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+
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switch (info->state) {
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case STATE_PIO_WRITING:
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- __raw_writesl(info->mmio_base + NDDB, info->data_buff,
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- DIV_ROUND_UP(info->data_size, 4));
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+ __raw_writesl(info->mmio_base + NDDB,
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+ info->data_buff + info->data_buff_pos,
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+ DIV_ROUND_UP(do_bytes, 4));
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+
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if (info->oob_size > 0)
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- __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
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- DIV_ROUND_UP(info->oob_size, 4));
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+ __raw_writesl(info->mmio_base + NDDB,
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+ info->oob_buff + info->oob_buff_pos,
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+ DIV_ROUND_UP(info->oob_size, 4));
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break;
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case STATE_PIO_READING:
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- __raw_readsl(info->mmio_base + NDDB, info->data_buff,
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- DIV_ROUND_UP(info->data_size, 4));
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+ __raw_readsl(info->mmio_base + NDDB,
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+ info->data_buff + info->data_buff_pos,
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+ DIV_ROUND_UP(do_bytes, 4));
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+
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if (info->oob_size > 0)
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- __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
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- DIV_ROUND_UP(info->oob_size, 4));
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+ __raw_readsl(info->mmio_base + NDDB,
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+ info->oob_buff + info->oob_buff_pos,
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+ DIV_ROUND_UP(info->oob_size, 4));
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break;
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default:
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dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
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info->state);
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BUG();
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}
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+
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+ /* Update buffer pointers for multi-page read/write */
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+ info->data_buff_pos += do_bytes;
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+ info->oob_buff_pos += info->oob_size;
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+ info->data_size -= do_bytes;
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}
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#ifdef ARCH_HAS_DMA
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@@ -616,6 +632,8 @@ static void prepare_start_command(struct
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info->buf_start = 0;
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info->buf_count = 0;
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info->oob_size = 0;
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+ info->data_buff_pos = 0;
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+ info->oob_buff_pos = 0;
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info->use_ecc = 0;
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info->use_spare = 1;
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info->retcode = ERR_NONE;
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@@ -626,7 +644,7 @@ static void prepare_start_command(struct
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case NAND_CMD_PAGEPROG:
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info->use_ecc = 1;
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case NAND_CMD_READOOB:
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- pxa3xx_set_datasize(info);
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+ pxa3xx_set_datasize(info, mtd);
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break;
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case NAND_CMD_PARAM:
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info->use_spare = 0;
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