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285 lines
7.0 KiB
C
285 lines
7.0 KiB
C
#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <linux/of_platform.h>
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#include <linux/clocksource.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/stmmac.h>
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#include <linux/slab.h>
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#include <linux/gfp.h>
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#include <linux/reset.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/mach/arch.h>
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#include <asm/page.h>
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#include <mach/iomap.h>
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#include <mach/hardware.h>
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#include <mach/utils.h>
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#include <mach/smp.h>
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static struct map_desc ox820_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)OXNAS_PERCPU_BASE_VA,
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.pfn = __phys_to_pfn(OXNAS_PERCPU_BASE),
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.length = OXNAS_PERCPU_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA,
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.pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE),
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.length = OXNAS_SYSCRTL_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA,
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.pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE),
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.length = OXNAS_SECCRTL_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long)OXNAS_RPSA_BASE_VA,
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.pfn = __phys_to_pfn(OXNAS_RPSA_BASE),
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.length = OXNAS_RPSA_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = (unsigned long)OXNAS_RPSC_BASE_VA,
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.pfn = __phys_to_pfn(OXNAS_RPSC_BASE),
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.length = OXNAS_RPSC_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init ox820_map_common_io(void)
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{
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debug_ll_io_init();
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iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc));
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}
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struct plat_gmac_data {
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struct plat_stmmacenet_data stmmac;
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struct clk *clk;
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};
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void *ox820_gmac_setup(struct platform_device *pdev)
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{
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struct plat_gmac_data *pdata = pdev->dev.platform_data;
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pdata->clk = clk_get(&pdev->dev, "gmac");
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return (void *) pdata->clk;
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};
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int ox820_gmac_init(struct platform_device *pdev, void *priv)
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{
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int ret;
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unsigned value;
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ret = device_reset(&pdev->dev);
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if (ret)
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return ret;
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if (IS_ERR(priv))
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return PTR_ERR(priv);
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clk_prepare_enable(priv);
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value = readl(SYS_CTRL_GMAC_CTRL);
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/* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */
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value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
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/* Use simple mux for 25/125 Mhz clock switching */
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value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
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/* set auto switch tx clock source */
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value |= BIT(SYS_CTRL_GMAC_AUTO_TX_SOURCE);
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/* enable tx & rx vardelay */
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value |= BIT(SYS_CTRL_GMAC_CKEN_TX_OUT);
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value |= BIT(SYS_CTRL_GMAC_CKEN_TXN_OUT);
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value |= BIT(SYS_CTRL_GMAC_CKEN_TX_IN);
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value |= BIT(SYS_CTRL_GMAC_CKEN_RX_OUT);
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value |= BIT(SYS_CTRL_GMAC_CKEN_RXN_OUT);
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value |= BIT(SYS_CTRL_GMAC_CKEN_RX_IN);
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writel(value, SYS_CTRL_GMAC_CTRL);
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/* set tx & rx vardelay */
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value = 0;
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value |= SYS_CTRL_GMAC_TX_VARDELAY(4);
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value |= SYS_CTRL_GMAC_TXN_VARDELAY(2);
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value |= SYS_CTRL_GMAC_RX_VARDELAY(10);
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value |= SYS_CTRL_GMAC_RXN_VARDELAY(8);
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writel(value, SYS_CTRL_GMAC_DELAY_CTRL);
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return 0;
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}
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void ox820_gmac_exit(struct platform_device *pdev, void *priv)
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{
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struct reset_control *rstc;
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clk_disable_unprepare(priv);
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clk_put(priv);
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rstc = reset_control_get(&pdev->dev, NULL);
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if (!IS_ERR(rstc)) {
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reset_control_assert(rstc);
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reset_control_put(rstc);
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}
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}
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static int __init ox820_ether_init(void)
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{
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struct device_node *node;
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struct platform_device *pdev;
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struct plat_gmac_data *pdata;
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node = of_find_compatible_node(NULL, NULL, "plxtech,nas782x-gmac");
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if (!node)
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return -ENOENT;
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pdev = of_find_device_by_node(node);
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of_node_put(node);
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if (!pdev)
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return -EINVAL;
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pdata = kzalloc(sizeof(struct plat_gmac_data), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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pdata->stmmac.setup = ox820_gmac_setup;
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pdata->stmmac.init = ox820_gmac_init;
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pdata->stmmac.exit = ox820_gmac_exit;
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pdev->dev.platform_data = pdata;
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return 0;
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}
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static void __init ox820_dt_init(void)
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{
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int ret;
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ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
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NULL);
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if (ret) {
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pr_err("of_platform_populate failed: %d\n", ret);
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BUG();
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}
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ret = ox820_ether_init();
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if (ret)
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pr_info("ox820_ether_init failed: %d\n", ret);
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}
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static void __init ox820_timer_init(void)
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{
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of_clk_init(NULL);
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clocksource_of_init();
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}
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void ox820_init_early(void)
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{
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}
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void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd)
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{
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u32 value;
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/* Assert reset to cores as per power on defaults
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* Don't touch the DDR interface as things will come to an impromptu stop
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* NB Possibly should be asserting reset for PLLB, but there are timing
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* concerns here according to the docs */
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value = BIT(SYS_CTRL_RST_COPRO) |
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BIT(SYS_CTRL_RST_USBHS) |
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BIT(SYS_CTRL_RST_USBHSPHYA) |
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BIT(SYS_CTRL_RST_MACA) |
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BIT(SYS_CTRL_RST_PCIEA) |
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BIT(SYS_CTRL_RST_SGDMA) |
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BIT(SYS_CTRL_RST_CIPHER) |
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BIT(SYS_CTRL_RST_SATA) |
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BIT(SYS_CTRL_RST_SATA_LINK) |
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BIT(SYS_CTRL_RST_SATA_PHY) |
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BIT(SYS_CTRL_RST_PCIEPHY) |
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BIT(SYS_CTRL_RST_STATIC) |
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BIT(SYS_CTRL_RST_UART1) |
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BIT(SYS_CTRL_RST_UART2) |
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BIT(SYS_CTRL_RST_MISC) |
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BIT(SYS_CTRL_RST_I2S) |
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BIT(SYS_CTRL_RST_SD) |
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BIT(SYS_CTRL_RST_MACB) |
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BIT(SYS_CTRL_RST_PCIEB) |
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BIT(SYS_CTRL_RST_VIDEO) |
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BIT(SYS_CTRL_RST_USBHSPHYB) |
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BIT(SYS_CTRL_RST_USBDEV);
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writel(value, SYS_CTRL_RST_SET_CTRL);
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/* Release reset to cores as per power on defaults */
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writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
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/* Disable clocks to cores as per power-on defaults - must leave DDR
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* related clocks enabled otherwise we'll stop rather abruptly. */
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value =
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BIT(SYS_CTRL_CLK_COPRO) |
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BIT(SYS_CTRL_CLK_DMA) |
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BIT(SYS_CTRL_CLK_CIPHER) |
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BIT(SYS_CTRL_CLK_SD) |
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BIT(SYS_CTRL_CLK_SATA) |
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BIT(SYS_CTRL_CLK_I2S) |
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BIT(SYS_CTRL_CLK_USBHS) |
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BIT(SYS_CTRL_CLK_MAC) |
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BIT(SYS_CTRL_CLK_PCIEA) |
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BIT(SYS_CTRL_CLK_STATIC) |
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BIT(SYS_CTRL_CLK_MACB) |
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BIT(SYS_CTRL_CLK_PCIEB) |
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BIT(SYS_CTRL_CLK_REF600) |
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BIT(SYS_CTRL_CLK_USBDEV);
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writel(value, SYS_CTRL_CLK_CLR_CTRL);
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/* Enable clocks to cores as per power-on defaults */
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/* Set sys-control pin mux'ing as per power-on defaults */
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writel(0, SYS_CTRL_SECONDARY_SEL);
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writel(0, SYS_CTRL_TERTIARY_SEL);
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writel(0, SYS_CTRL_QUATERNARY_SEL);
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writel(0, SYS_CTRL_DEBUG_SEL);
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writel(0, SYS_CTRL_ALTERNATIVE_SEL);
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writel(0, SYS_CTRL_PULLUP_SEL);
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writel(0, SYS_CTRL_SECONDARY_SEL);
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writel(0, SYS_CTRL_TERTIARY_SEL);
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writel(0, SYS_CTRL_QUATERNARY_SEL);
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writel(0, SYS_CTRL_DEBUG_SEL);
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writel(0, SYS_CTRL_ALTERNATIVE_SEL);
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writel(0, SYS_CTRL_PULLUP_SEL);
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/* No need to save any state, as the ROM loader can determine whether
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* reset is due to power cycling or programatic action, just hit the
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* (self-clearing) CPU reset bit of the block reset register */
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value =
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BIT(SYS_CTRL_RST_SCU) |
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BIT(SYS_CTRL_RST_ARM0) |
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BIT(SYS_CTRL_RST_ARM1);
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writel(value, SYS_CTRL_RST_SET_CTRL);
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}
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static const char * const ox820_dt_board_compat[] = {
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"plxtech,nas7820",
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"plxtech,nas7821",
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"plxtech,nas7825",
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NULL
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};
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DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)")
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.map_io = ox820_map_common_io,
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.smp = smp_ops(ox820_smp_ops),
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.init_early = ox820_init_early,
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.init_time = ox820_timer_init,
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.init_machine = ox820_dt_init,
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.restart = ox820_assert_system_reset,
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.dt_compat = ox820_dt_board_compat,
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MACHINE_END
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