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484 lines
13 KiB
Diff
484 lines
13 KiB
Diff
--- /dev/null
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+++ b/arch/arm/plat-s3c24xx/time.c
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@@ -0,0 +1,480 @@
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+/* linux/arch/arm/plat-s3c24xx/time.c
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+ *
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+ * Copyright (C) 2003-2005 Simtec Electronics
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+ * Ben Dooks, <ben@simtec.co.uk>
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+ *
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+ * dyn_tick support by Andrzej Zaborowski based on omap_dyn_tick_timer.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/sched.h>
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/irq.h>
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+#include <linux/err.h>
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+#include <linux/clk.h>
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+
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+#include <asm/system.h>
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+#include <asm/leds.h>
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+#include <asm/mach-types.h>
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+
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+#include <asm/io.h>
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+#include <asm/irq.h>
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+#include <mach/map.h>
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+#include <asm/plat-s3c/regs-timer.h>
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+#include <mach/regs-irq.h>
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+#include <asm/mach/time.h>
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+
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+#include <asm/plat-s3c24xx/clock.h>
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+#include <asm/plat-s3c24xx/cpu.h>
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+
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+static unsigned long timer_startval;
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+static unsigned long timer_usec_ticks;
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+static struct work_struct resume_work;
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+
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+unsigned long pclk;
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+struct clk *clk;
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+
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+#define TIMER_USEC_SHIFT 16
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+
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+/* we use the shifted arithmetic to work out the ratio of timer ticks
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+ * to usecs, as often the peripheral clock is not a nice even multiple
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+ * of 1MHz.
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+ *
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+ * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
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+ * for the current HZ value of 200 without producing overflows.
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+ *
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+ * Original patch by Dimitry Andric, updated by Ben Dooks
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+*/
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+
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+
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+/* timer_mask_usec_ticks
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+ *
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+ * given a clock and divisor, make the value to pass into timer_ticks_to_usec
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+ * to scale the ticks into usecs
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+*/
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+
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+static inline unsigned long
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+timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
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+{
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+ unsigned long den = pclk / 1000;
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+
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+ return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
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+}
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+
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+/* timer_ticks_to_usec
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+ *
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+ * convert timer ticks to usec.
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+*/
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+
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+static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
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+{
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+ unsigned long res;
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+
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+ res = ticks * timer_usec_ticks;
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+ res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
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+
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+ return res >> TIMER_USEC_SHIFT;
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+}
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+
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+/***
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+ * Returns microsecond since last clock interrupt. Note that interrupts
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+ * will have been disabled by do_gettimeoffset()
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+ * IRQs are disabled before entering here from do_gettimeofday()
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+ */
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+
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+#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
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+
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+unsigned long s3c2410_gettimeoffset (void)
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+{
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+ unsigned long tdone;
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+ unsigned long irqpend;
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+ unsigned long tval;
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+
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+ /* work out how many ticks have gone since last timer interrupt */
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+
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+ tval = __raw_readl(S3C2410_TCNTO(4));
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+ tdone = timer_startval - tval;
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+
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+ /* check to see if there is an interrupt pending */
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+
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+ irqpend = __raw_readl(S3C2410_SRCPND);
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+ if (irqpend & SRCPND_TIMER4) {
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+ /* re-read the timer, and try and fix up for the missed
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+ * interrupt. Note, the interrupt may go off before the
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+ * timer has re-loaded from wrapping.
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+ */
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+
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+ tval = __raw_readl(S3C2410_TCNTO(4));
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+ tdone = timer_startval - tval;
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+
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+ if (tval != 0)
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+ tdone += timer_startval;
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+ }
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+
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+ return timer_ticks_to_usec(tdone);
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+}
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+
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+
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+/*
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+ * IRQ handler for the timer
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+ */
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+static irqreturn_t
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+s3c2410_timer_interrupt(int irq, void *dev_id)
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+{
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+ timer_tick();
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction s3c2410_timer_irq = {
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+ .name = "S3C2410 Timer Tick",
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+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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+ .handler = s3c2410_timer_interrupt,
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+};
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+
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+#define use_tclk1_12() ( \
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+ machine_is_bast() || \
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+ machine_is_vr1000() || \
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+ machine_is_anubis() || \
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+ machine_is_osiris() )
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+
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+/*
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+ * Set up timer interrupt, and return the current time in seconds.
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+ *
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+ * Currently we only use timer4, as it is the only timer which has no
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+ * other function that can be exploited externally
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+ */
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+static void s3c2410_timer_setup (void)
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+{
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+ unsigned long tcon;
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+ unsigned long tcnt;
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+ unsigned long tcfg1;
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+ unsigned long tcfg0;
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+
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+ tcnt = 0xffff; /* default value for tcnt */
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+
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+ /* read the current timer configuration bits */
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+
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+ tcon = __raw_readl(S3C2410_TCON);
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+ tcfg1 = __raw_readl(S3C2410_TCFG1);
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+ tcfg0 = __raw_readl(S3C2410_TCFG0);
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+
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+ /* configure the system for whichever machine is in use */
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+
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+ if (use_tclk1_12()) {
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+ /* timer is at 12MHz, scaler is 1 */
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+ timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
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+ tcnt = 12000000 / HZ;
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+
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+ tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
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+ tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
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+ } else {
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+ /* since values around 50 to
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+ * 70MHz are not values we can directly generate the timer
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+ * value from, we need to pre-scale and divide before using it.
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+ *
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+ * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
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+ * (8.45 ticks per usec)
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+ */
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+
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+ /* configure clock tick */
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+ timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
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+ printk("timer_usec_ticks = %lu\n", timer_usec_ticks);
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+
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+ tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
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+ tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
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+
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+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
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+ tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
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+
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+ tcnt = (pclk / 6) / HZ;
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+ }
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+
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+ /* timers reload after counting zero, so reduce the count by 1 */
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+
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+ tcnt--;
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+
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+ printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
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+ tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
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+
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+ /* check to see if timer is within 16bit range... */
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+ if (tcnt > 0xffff) {
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+ panic("setup_timer: HZ is too small, cannot configure timer!");
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+ return;
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+ }
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+
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+ __raw_writel(tcfg1, S3C2410_TCFG1);
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+ __raw_writel(tcfg0, S3C2410_TCFG0);
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+
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+ timer_startval = tcnt;
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+ __raw_writel(tcnt, S3C2410_TCNTB(4));
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+
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+ /* ensure timer is stopped... */
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+
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+ tcon &= ~(7<<20);
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+ tcon |= S3C2410_TCON_T4RELOAD;
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+ tcon |= S3C2410_TCON_T4MANUALUPD;
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+
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+ __raw_writel(tcon, S3C2410_TCON);
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+ __raw_writel(tcnt, S3C2410_TCNTB(4));
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+ __raw_writel(tcnt, S3C2410_TCMPB(4));
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+
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+ /* start the timer running */
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+ tcon |= S3C2410_TCON_T4START;
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+ tcon &= ~S3C2410_TCON_T4MANUALUPD;
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+ __raw_writel(tcon, S3C2410_TCON);
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+
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+ __raw_writel(__raw_readl(S3C2410_INTMSK) & (~(1UL << 14)),
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+ S3C2410_INTMSK);
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+
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+}
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+
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+struct sys_timer s3c24xx_timer;
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+static void timer_resume_work(struct work_struct *work)
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+{
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+ clk_enable(clk);
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+
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+#ifdef CONFIG_NO_IDLE_HZ
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+ if (s3c24xx_timer.dyn_tick->state & DYN_TICK_ENABLED)
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+ s3c24xx_timer.dyn_tick->enable();
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+ else
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+#endif
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+ s3c2410_timer_setup();
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+}
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+
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+static void __init s3c2410_timer_init (void)
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+{
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+ if (!use_tclk1_12()) {
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+ /* for the h1940 (and others), we use the pclk from the core
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+ * to generate the timer values.
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+ */
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+
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+ /* this is used as default if no other timer can be found */
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+ clk = clk_get(NULL, "timers");
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+ if (IS_ERR(clk))
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+ panic("failed to get clock for system timer");
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+
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+ clk_enable(clk);
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+
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+ pclk = clk_get_rate(clk);
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+ printk("pclk = %lu\n", pclk);
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+ }
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+
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+ INIT_WORK(&resume_work, timer_resume_work);
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+ s3c2410_timer_setup();
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+ setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
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+}
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+
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+static void s3c2410_timer_resume_work(struct work_struct *work)
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+{
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+ s3c2410_timer_setup();
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+}
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+
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+static void s3c2410_timer_resume(void)
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+{
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+ static DECLARE_WORK(work, s3c2410_timer_resume_work);
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+ int res;
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+
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+ res = schedule_work(&work);
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+ if (!res)
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+ printk(KERN_ERR
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+ "s3c2410_timer_resume_work already queued ???\n");
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+}
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+
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+#ifdef CONFIG_NO_IDLE_HZ
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+/*
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+ * We'll set a constant prescaler so we don't have to bother setting it
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+ * when reprogramming and so that we avoid costly divisions.
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+ *
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+ * (2 * HZ) << INPUT_FREQ_SHIFT is the desired frequency after prescaler.
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+ * At HZ == 200, HZ * 1024 should work for PCLKs of up to ~53.5 MHz.
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+ */
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+#define INPUT_FREQ_SHIFT 9
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+
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+static int ticks_last;
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+static int ticks_left;
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+static uint32_t tcnto_last;
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+
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+static inline int s3c24xx_timer_read(void)
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+{
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+ uint32_t tcnto = __raw_readl(S3C2410_TCNTO(4));
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+
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+ /*
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+ * WARNING: sometimes we get called before TCNTB has been
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+ * loaded into the counter and TCNTO then returns its previous
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+ * value and kill us, so don't do anything before counter is
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+ * reloaded.
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+ */
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+ if (unlikely(tcnto == tcnto_last))
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+ return ticks_last;
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+
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+ tcnto_last = -1;
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+ return tcnto <<
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+ ((__raw_readl(S3C2410_TCFG1) >> S3C2410_TCFG1_MUX4_SHIFT) & 3);
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+}
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+
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+static inline void s3c24xx_timer_program(int ticks)
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+{
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+ uint32_t tcon = __raw_readl(S3C2410_TCON) & ~(7 << 20);
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+ uint32_t tcfg1 = __raw_readl(S3C2410_TCFG1) & ~S3C2410_TCFG1_MUX4_MASK;
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+
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+ /* Just make sure the timer is stopped. */
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+ __raw_writel(tcon, S3C2410_TCON);
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+
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+ /* TODO: add likely()ies / unlikely()ies */
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+ if (ticks >> 18) {
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+ ticks_last = min(ticks, 0xffff << 3);
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+ ticks_left = ticks - ticks_last;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV16, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 3, S3C2410_TCNTB(4));
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+ } else if (ticks >> 17) {
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+ ticks_last = ticks;
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+ ticks_left = 0;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV8, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 2, S3C2410_TCNTB(4));
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+ } else if (ticks >> 16) {
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+ ticks_last = ticks;
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+ ticks_left = 0;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV4, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 1, S3C2410_TCNTB(4));
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+ } else {
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+ ticks_last = ticks;
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+ ticks_left = 0;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV2, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 0, S3C2410_TCNTB(4));
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+ }
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+
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+ tcnto_last = __raw_readl(S3C2410_TCNTO(4));
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+ __raw_writel(tcon | S3C2410_TCON_T4MANUALUPD,
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+ S3C2410_TCON);
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+ __raw_writel(tcon | S3C2410_TCON_T4START,
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+ S3C2410_TCON);
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+}
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+
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+/*
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+ * If we have already waited all the time we were supposed to wait,
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+ * kick the timer, setting the longest allowed timeout value just
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+ * for time-keeping.
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+ */
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+static inline void s3c24xx_timer_program_idle(void)
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+{
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+ s3c24xx_timer_program(0xffff << 3);
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+}
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+
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+static inline void s3c24xx_timer_update(int restart)
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+{
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+ int ticks_cur = s3c24xx_timer_read();
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+ int jiffies_elapsed = (ticks_last - ticks_cur) >> INPUT_FREQ_SHIFT;
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+ int subjiffy = ticks_last - (jiffies_elapsed << INPUT_FREQ_SHIFT);
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+
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+ if (restart) {
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+ if (ticks_left >= (1 << INPUT_FREQ_SHIFT))
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+ s3c24xx_timer_program(ticks_left);
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+ else
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+ s3c24xx_timer_program_idle();
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+ ticks_last += subjiffy;
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+ } else
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+ ticks_last = subjiffy;
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+
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+ while (jiffies_elapsed --)
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+ timer_tick();
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+}
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+
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+/* Called when the timer expires. */
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+static irqreturn_t s3c24xx_timer_handler(int irq, void *dev_id)
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+{
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+ tcnto_last = -1;
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+ s3c24xx_timer_update(1);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+/* Called to update jiffies with time elapsed. */
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+static irqreturn_t s3c24xx_timer_handler_dyn_tick(int irq, void *dev_id)
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+{
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+ s3c24xx_timer_update(0);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+/*
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+ * Programs the next timer interrupt needed. Called when dynamic tick is
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+ * enabled, and to reprogram the ticks to skip from pm_idle. The CPU goes
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+ * to sleep directly after this.
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+ */
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+static void s3c24xx_timer_reprogram_dyn_tick(unsigned long next_jiffies)
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+{
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+ int subjiffy_left = ticks_last - s3c24xx_timer_read();
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+
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+ s3c24xx_timer_program(max((int) next_jiffies, 1) << INPUT_FREQ_SHIFT);
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+ ticks_last += subjiffy_left;
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+}
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+
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+static unsigned long s3c24xx_timer_offset_dyn_tick(void)
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+{
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+ /* TODO */
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+ return 0;
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+}
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+
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+static int s3c24xx_timer_enable_dyn_tick(void)
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+{
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+ /* Set our constant prescaler. */
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+ uint32_t tcfg0 = __raw_readl(S3C2410_TCFG0);
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+ int prescaler =
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+ max(min(256, (int) pclk / (HZ << (INPUT_FREQ_SHIFT + 1))), 1);
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+
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+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
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+ tcfg0 |= (prescaler - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
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+ __raw_writel(tcfg0, S3C2410_TCFG0);
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+
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+ /* Override handlers. */
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+ s3c2410_timer_irq.handler = s3c24xx_timer_handler;
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+ s3c24xx_timer.offset = s3c24xx_timer_offset_dyn_tick;
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+
|
|
+ printk(KERN_INFO "dyn_tick enabled on s3c24xx timer 4, "
|
|
+ "%li Hz pclk with prescaler %i\n", pclk, prescaler);
|
|
+
|
|
+ s3c24xx_timer_program_idle();
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int s3c24xx_timer_disable_dyn_tick(void)
|
|
+{
|
|
+ s3c2410_timer_irq.handler = s3c2410_timer_interrupt;
|
|
+ s3c24xx_timer.offset = s3c2410_gettimeoffset;
|
|
+ s3c2410_timer_setup();
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct dyn_tick_timer s3c24xx_dyn_tick_timer = {
|
|
+ .enable = s3c24xx_timer_enable_dyn_tick,
|
|
+ .disable = s3c24xx_timer_disable_dyn_tick,
|
|
+ .reprogram = s3c24xx_timer_reprogram_dyn_tick,
|
|
+ .handler = s3c24xx_timer_handler_dyn_tick,
|
|
+};
|
|
+#endif /* CONFIG_NO_IDLE_HZ */
|
|
+
|
|
+struct sys_timer s3c24xx_timer = {
|
|
+ .init = s3c2410_timer_init,
|
|
+ .offset = s3c2410_gettimeoffset,
|
|
+ .resume = s3c2410_timer_resume,
|
|
+#ifdef CONFIG_NO_IDLE_HZ
|
|
+ .dyn_tick = &s3c24xx_dyn_tick_timer,
|
|
+#endif
|
|
+};
|