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104 lines
2.3 KiB
Diff
104 lines
2.3 KiB
Diff
From c2046901f933b0e1c87c5cbdab4ba27a3b66317e Mon Sep 17 00:00:00 2001
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From: Pankaj Bansal <pankaj.bansal@nxp.com>
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Date: Wed, 8 May 2019 17:49:14 +0530
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Subject: [PATCH] arm64: dts: fsl: lx2160a: add flexcan node
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Add flexcan node in LX2160A SOC file as well as in QDS and RDB files.
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The device tree bindings used can be referred from
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Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
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Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 10 +++++++++-
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arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 18 +++++++++++++++++-
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arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 18 ++++++++++++++++++
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3 files changed, 44 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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@@ -2,7 +2,7 @@
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//
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// Device Tree file for LX2160AQDS
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//
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-// Copyright 2018 NXP
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+// Copyright 2018-2019 NXP
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/dts-v1/;
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@@ -155,6 +155,14 @@
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};
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};
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+&can0 {
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+ status = "okay";
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+};
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+
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+&can1 {
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+ status = "okay";
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+};
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+
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&crypto {
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status = "okay";
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
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@@ -2,7 +2,7 @@
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//
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// Device Tree file for LX2160ARDB
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//
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-// Copyright 2018 NXP
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+// Copyright 2018-2019 NXP
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/dts-v1/;
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@@ -31,6 +31,22 @@
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};
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};
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+&can0 {
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+ status = "okay";
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+
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+ can-transceiver {
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+ max-bitrate = <5000000>;
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+ };
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+};
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+
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+&can1 {
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+ status = "okay";
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+
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+ can-transceiver {
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+ max-bitrate = <5000000>;
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+ };
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+};
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+
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&crypto {
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status = "okay";
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
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@@ -753,6 +753,24 @@
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status = "disabled";
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};
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+ can0: can@2180000 {
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+ compatible = "fsl,lx2160ar1-flexcan";
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+ reg = <0x0 0x2180000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&sysclk>, <&clockgen 4 7>;
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+ clock-names = "ipg", "per";
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+ status = "disabled";
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+ };
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+
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+ can1: can@2190000 {
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+ compatible = "fsl,lx2160ar1-flexcan";
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+ reg = <0x0 0x2190000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&sysclk>, <&clockgen 4 7>;
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+ clock-names = "ipg", "per";
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+ status = "disabled";
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+ };
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+
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uart0: serial@21c0000 {
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compatible = "arm,sbsa-uart","arm,pl011";
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reg = <0x0 0x21c0000 0x0 0x1000>;
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