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285 lines
7.2 KiB
Diff
285 lines
7.2 KiB
Diff
The Armada XP SoCs have multiple PCIe interfaces. The MV78230 has 2
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PCIe units (one 4x or quad 1x, the other 1x only), the MV78260 has 3
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PCIe units (two 4x or quad 1x and one 4x/1x), the MV78460 has 4 PCIe
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units (two 4x or quad 1x and two 4x/1x). We therefore add the
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necessary Device Tree informations to make those PCIe interfaces
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usable.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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arch/arm/boot/dts/armada-xp-mv78230.dtsi | 62 +++++++++++++++++
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arch/arm/boot/dts/armada-xp-mv78260.dtsi | 72 +++++++++++++++++++
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arch/arm/boot/dts/armada-xp-mv78460.dtsi | 112 ++++++++++++++++++++++++++++++
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3 files changed, 246 insertions(+)
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--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
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+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
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@@ -76,5 +76,67 @@
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#interrupts-cells = <2>;
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interrupts = <87>, <88>, <89>;
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};
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+
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+ /*
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+ * MV78230 has 2 PCIe units Gen2.0: One unit can be
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+ * configured as x4 or quad x1 lanes. One unit is
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+ * x4/x1.
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+ */
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+ pcie-controller {
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+ compatible = "marvell,armada-370-xp-pcie";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
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+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
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+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
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+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
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+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */>;
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+
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+ pcie0.0@0xd0040000 {
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+ reg = <0x0 0x2000>;
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+ interrupts = <58>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.1@0xd0044000 {
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+ reg = <0x4000 0x2000>;
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+ interrupts = <59>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <1>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.2@0xd0048000 {
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+ reg = <0x8000 0x2000>;
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+ interrupts = <60>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <2>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.3@0xd004C000 {
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+ reg = <0xC000 0x2000>;
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+ interrupts = <61>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <3>;
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+ status = "disabled";
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+ };
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+
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+ pcie2@0xd0042000 {
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+ reg = <0x2000 0x2000>;
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+ interrupts = <99>;
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+ clocks = <&gateclk 7>;
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+ marvell,pcie-port = <2>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+ };
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};
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};
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--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
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+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
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@@ -96,5 +96,77 @@
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clocks = <&gateclk 1>;
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status = "disabled";
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};
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+
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+ /*
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+ * MV78260 has 3 PCIe units Gen2.0: Two units can be
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+ * configured as x4 or quad x1 lanes. One unit is
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+ * x4/x1.
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+ */
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+ pcie-controller {
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+ compatible = "marvell,armada-370-xp-pcie";
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+ status = "okay";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
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+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
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+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
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+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
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+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
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+ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */>;
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+
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+ pcie0.0@0xd0040000 {
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+ reg = <0x0 0x2000>;
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+ interrupts = <58>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.1@0xd0044000 {
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+ reg = <0x4000 0x2000>;
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+ interrupts = <59>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <1>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.2@0xd0048000 {
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+ reg = <0x8000 0x2000>;
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+ interrupts = <60>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <2>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.3@0xd004C000 {
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+ reg = <0xC000 0x2000>;
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+ interrupts = <61>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <3>;
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+ status = "disabled";
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+ };
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+
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+ pcie2@0xd0042000 {
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+ reg = <0x2000 0x2000>;
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+ interrupts = <99>;
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+ clocks = <&gateclk 7>;
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+ marvell,pcie-port = <2>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie3@0xd0082000 {
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+ reg = <0x12000 0x2000>;
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+ interrupts = <103>;
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+ clocks = <&gateclk 8>;
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+ marvell,pcie-port = <3>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+ };
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};
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};
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--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
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+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
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@@ -111,5 +111,117 @@
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clocks = <&gateclk 1>;
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status = "disabled";
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};
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+
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+ /*
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+ * MV78460 has 4 PCIe units Gen2.0: Two units can be
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+ * configured as x4 or quad x1 lanes. Two units are
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+ * x4/x1.
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+ */
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+ pcie-controller {
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+ compatible = "marvell,armada-370-xp-pcie";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0xd0040000 0x2000 /* port0x1_port0 */
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+ 0x2000 0xd0042000 0x2000 /* port2x1_port0 */
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+ 0x4000 0xd0044000 0x2000 /* port0x1_port1 */
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+ 0x8000 0xd0048000 0x2000 /* port0x1_port2 */
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+ 0xC000 0xd004C000 0x2000 /* port0x1_port3 */
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+ 0x10000 0xd0080000 0x2000 /* port1x1_port0 */
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+ 0x12000 0xd0082000 0x2000 /* port3x1_port0 */
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+ 0x14000 0xd0084000 0x2000 /* port1x1_port1 */
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+ 0x18000 0xd0088000 0x2000 /* port1x1_port2 */
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+ 0x1C000 0xd008C000 0x2000 /* port1x1_port3 */>;
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+
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+ pcie0.0@0xd0040000 {
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+ reg = <0x0 0x2000>;
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+ interrupts = <58>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.1@0xd0044000 {
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+ reg = <0x4000 0x2000>;
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+ interrupts = <59>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <1>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.2@0xd0048000 {
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+ reg = <0x8000 0x2000>;
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+ interrupts = <60>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <2>;
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+ status = "disabled";
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+ };
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+
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+ pcie0.3@0xd004C000 {
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+ reg = <0xC000 0x2000>;
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+ interrupts = <61>;
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+ clocks = <&gateclk 5>;
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+ marvell,pcie-port = <0>;
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+ marvell,pcie-lane = <3>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.0@0xd0040000 {
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+ reg = <0x10000 0x2000>;
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+ interrupts = <62>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.1@0xd0044000 {
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+ reg = <0x14000 0x2000>;
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+ interrupts = <63>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <1>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.2@0xd0048000 {
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+ reg = <0x18000 0x2000>;
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+ interrupts = <64>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <2>;
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+ status = "disabled";
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+ };
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+
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+ pcie1.3@0xd004C000 {
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+ reg = <0x1C000 0x2000>;
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+ interrupts = <65>;
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+ clocks = <&gateclk 6>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <3>;
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+ status = "disabled";
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+ };
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+
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+ pcie2@0xd0042000 {
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+ reg = <0x2000 0x2000>;
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+ interrupts = <99>;
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+ clocks = <&gateclk 7>;
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+ marvell,pcie-port = <2>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+
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+ pcie3@0xd0082000 {
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+ reg = <0x12000 0x2000>;
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+ interrupts = <103>;
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+ clocks = <&gateclk 8>;
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+ marvell,pcie-port = <3>;
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+ marvell,pcie-lane = <0>;
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+ status = "disabled";
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+ };
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+ };
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};
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};
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