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83 lines
2.7 KiB
Diff
83 lines
2.7 KiB
Diff
Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Subject: [v3,3/5] dt/bindings: qcom_nandc: Add DT bindings
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From: Archit Taneja <architt@codeaurora.org>
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X-Patchwork-Id: 6927141
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Message-Id: <1438578498-32254-4-git-send-email-architt@codeaurora.org>
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To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
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cernekee@gmail.com, computersforpeace@gmail.com
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Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
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sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
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Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
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Date: Mon, 3 Aug 2015 10:38:16 +0530
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Add DT bindings document for the Qualcomm NAND controller driver.
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Cc: devicetree@vger.kernel.org
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v3:
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- Don't use '0x' when specifying nand controller address space
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- Add optional property for on-flash bbt usage
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Acked-by: Andy Gross <agross@codeaurora.org>
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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---
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.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++
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1 file changed, 49 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
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@@ -0,0 +1,49 @@
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+* Qualcomm NAND controller
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+
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+Required properties:
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+- compatible: should be "qcom,ebi2-nand" for IPQ806x
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+- reg: MMIO address range
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+- clocks: must contain core clock and always on clock
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+- clock-names: must contain "core" for the core clock and "aon" for the
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+ always on clock
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+- dmas: DMA specifier, consisting of a phandle to the ADM DMA
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+ controller node and the channel number to be used for
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+ NAND. Refer to dma.txt and qcom_adm.txt for more details
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+- dma-names: must be "rxtx"
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+- qcom,cmd-crci: must contain the ADM command type CRCI block instance
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+ number specified for the NAND controller on the given
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+ platform
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+- qcom,data-crci: must contain the ADM data type CRCI block instance
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+ number specified for the NAND controller on the given
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+ platform
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+
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+Optional properties:
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+- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen
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+ as default
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+
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+- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8
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+ bits. If not present, 4 is chosen as default
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+- nand-on-flash-bbt: Create/use on-flash bad block table
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+
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+The device tree may optionally contain sub-nodes describing partitions of the
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+address space. See partition.txt for more detail.
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+
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+Example:
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+
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+nand@1ac00000 {
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+ compatible = "qcom,ebi2-nandc";
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+ reg = <0x1ac00000 0x800>;
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+
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+ clocks = <&gcc EBI2_CLK>,
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+ <&gcc EBI2_AON_CLK>;
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+ clock-names = "core", "aon";
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+
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+ dmas = <&adm_dma 3>;
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+ dma-names = "rxtx";
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+ qcom,cmd-crci = <15>;
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+ qcom,data-crci = <3>;
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+
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+ partition@0 {
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+ ...
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+ };
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+};
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