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37 lines
1.3 KiB
Diff
37 lines
1.3 KiB
Diff
From 54eece496d38fb701d9719169d9270d8798191cc Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 11:39:20 +0000
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Subject: [PATCH 258/304] clk: bcm2835: divider value has to be 1 or more
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Current clamping of a normal divider allows a value < 1 to be valid.
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A divider of < 1 would actually only be possible if we had a PLL...
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So this patch clamps the divider to 1.
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Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
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audio domain clocks")
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e)
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---
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drivers/clk/bcm/clk-bcm2835.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1202,8 +1202,9 @@ static u32 bcm2835_clock_choose_div(stru
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div += unused_frac_mask + 1;
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div &= ~unused_frac_mask;
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- /* Clamp to the limits. */
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- div = max(div, unused_frac_mask + 1);
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+ /* clamp to min divider of 1 */
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+ div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
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+ /* clamp to the highest possible fractional divider */
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div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
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CM_DIV_FRAC_BITS - data->frac_bits));
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