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346 lines
10 KiB
Diff
346 lines
10 KiB
Diff
From 5042cf1359c0e6a3d3bf3c16935495dd7de0d0e4 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Tue, 8 Dec 2015 14:00:43 -0800
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Subject: [PATCH 117/304] drm/vc4: A few more non-functional changes to sync to
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upstream.
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At this point all that's left is the force-enable of HDMI connector,
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and using direct firmware calls to turn on V3D instead of the generic
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power domain support.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/gpu/drm/vc4/vc4_v3d.c | 2 +-
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include/uapi/drm/vc4_drm.h | 182 +++++++++++++++++++++---------------------
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2 files changed, 92 insertions(+), 92 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_v3d.c
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+++ b/drivers/gpu/drm/vc4/vc4_v3d.c
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@@ -109,7 +109,7 @@ static const struct {
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int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused)
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{
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- struct drm_info_node *node = (struct drm_info_node *) m->private;
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+ struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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int i;
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--- a/include/uapi/drm/vc4_drm.h
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+++ b/include/uapi/drm/vc4_drm.h
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@@ -24,7 +24,7 @@
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#ifndef _UAPI_VC4_DRM_H_
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#define _UAPI_VC4_DRM_H_
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-#include <drm/drm.h>
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+#include "drm.h"
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#define DRM_VC4_SUBMIT_CL 0x00
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#define DRM_VC4_WAIT_SEQNO 0x01
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@@ -34,25 +34,25 @@
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#define DRM_VC4_CREATE_SHADER_BO 0x05
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#define DRM_VC4_GET_HANG_STATE 0x06
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-#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
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-#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
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-#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
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-#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
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-#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
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-#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
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-#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
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+#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
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+#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
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+#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
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+#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
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+#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
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+#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
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+#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
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struct drm_vc4_submit_rcl_surface {
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- uint32_t hindex; /* Handle index, or ~0 if not present. */
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- uint32_t offset; /* Offset to start of buffer. */
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+ __u32 hindex; /* Handle index, or ~0 if not present. */
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+ __u32 offset; /* Offset to start of buffer. */
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/*
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- * Bits for either render config (color_write) or load/store packet.
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- * Bits should all be 0 for MSAA load/stores.
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+ * Bits for either render config (color_write) or load/store packet.
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+ * Bits should all be 0 for MSAA load/stores.
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*/
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- uint16_t bits;
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+ __u16 bits;
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#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
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- uint16_t flags;
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+ __u16 flags;
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};
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/**
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@@ -76,7 +76,7 @@ struct drm_vc4_submit_cl {
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* then writes out the state updates and draw calls necessary per tile
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* to the tile allocation BO.
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*/
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- uint64_t bin_cl;
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+ __u64 bin_cl;
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/* Pointer to the shader records.
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*
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@@ -85,16 +85,16 @@ struct drm_vc4_submit_cl {
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* reference to the shader record has enough information to determine
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* how many pointers are necessary (fixed number for shaders/uniforms,
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* and an attribute count), so those BO indices into bo_handles are
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- * just stored as uint32_ts before each shader record passed in.
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+ * just stored as __u32s before each shader record passed in.
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*/
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- uint64_t shader_rec;
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+ __u64 shader_rec;
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/* Pointer to uniform data and texture handles for the textures
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* referenced by the shader.
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*
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* For each shader state record, there is a set of uniform data in the
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* order referenced by the record (FS, VS, then CS). Each set of
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- * uniform data has a uint32_t index into bo_handles per texture
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+ * uniform data has a __u32 index into bo_handles per texture
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* sample operation, in the order the QPU_W_TMUn_S writes appear in
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* the program. Following the texture BO handle indices is the actual
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* uniform data.
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@@ -103,52 +103,52 @@ struct drm_vc4_submit_cl {
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* because the kernel has to determine the sizes anyway during shader
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* code validation.
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*/
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- uint64_t uniforms;
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- uint64_t bo_handles;
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+ __u64 uniforms;
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+ __u64 bo_handles;
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/* Size in bytes of the binner command list. */
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- uint32_t bin_cl_size;
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+ __u32 bin_cl_size;
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/* Size in bytes of the set of shader records. */
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- uint32_t shader_rec_size;
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+ __u32 shader_rec_size;
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/* Number of shader records.
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*
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* This could just be computed from the contents of shader_records and
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* the address bits of references to them from the bin CL, but it
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* keeps the kernel from having to resize some allocations it makes.
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*/
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- uint32_t shader_rec_count;
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+ __u32 shader_rec_count;
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/* Size in bytes of the uniform state. */
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- uint32_t uniforms_size;
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+ __u32 uniforms_size;
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/* Number of BO handles passed in (size is that times 4). */
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- uint32_t bo_handle_count;
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+ __u32 bo_handle_count;
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/* RCL setup: */
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- uint16_t width;
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- uint16_t height;
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- uint8_t min_x_tile;
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- uint8_t min_y_tile;
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- uint8_t max_x_tile;
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- uint8_t max_y_tile;
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+ __u16 width;
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+ __u16 height;
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+ __u8 min_x_tile;
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+ __u8 min_y_tile;
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+ __u8 max_x_tile;
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+ __u8 max_y_tile;
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struct drm_vc4_submit_rcl_surface color_read;
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struct drm_vc4_submit_rcl_surface color_write;
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struct drm_vc4_submit_rcl_surface zs_read;
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struct drm_vc4_submit_rcl_surface zs_write;
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struct drm_vc4_submit_rcl_surface msaa_color_write;
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struct drm_vc4_submit_rcl_surface msaa_zs_write;
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- uint32_t clear_color[2];
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- uint32_t clear_z;
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- uint8_t clear_s;
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+ __u32 clear_color[2];
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+ __u32 clear_z;
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+ __u8 clear_s;
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- uint32_t pad:24;
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+ __u32 pad:24;
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#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
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- uint32_t flags;
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+ __u32 flags;
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/* Returned value of the seqno of this render job (for the
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* wait ioctl).
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*/
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- uint64_t seqno;
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+ __u64 seqno;
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};
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/**
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@@ -159,8 +159,8 @@ struct drm_vc4_submit_cl {
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* block, just return the status."
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*/
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struct drm_vc4_wait_seqno {
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- uint64_t seqno;
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- uint64_t timeout_ns;
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+ __u64 seqno;
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+ __u64 timeout_ns;
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};
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/**
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@@ -172,9 +172,9 @@ struct drm_vc4_wait_seqno {
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* completed.
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*/
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struct drm_vc4_wait_bo {
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- uint32_t handle;
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- uint32_t pad;
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- uint64_t timeout_ns;
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+ __u32 handle;
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+ __u32 pad;
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+ __u64 timeout_ns;
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};
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/**
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@@ -184,11 +184,30 @@ struct drm_vc4_wait_bo {
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* used in a future extension.
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*/
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struct drm_vc4_create_bo {
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- uint32_t size;
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- uint32_t flags;
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+ __u32 size;
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+ __u32 flags;
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/** Returned GEM handle for the BO. */
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- uint32_t handle;
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- uint32_t pad;
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+ __u32 handle;
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+ __u32 pad;
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+};
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+
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+/**
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+ * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
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+ *
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+ * This doesn't actually perform an mmap. Instead, it returns the
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+ * offset you need to use in an mmap on the DRM device node. This
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+ * means that tools like valgrind end up knowing about the mapped
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+ * memory.
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+ *
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+ * There are currently no values for the flags argument, but it may be
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+ * used in a future extension.
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+ */
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+struct drm_vc4_mmap_bo {
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+ /** Handle for the object being mapped. */
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+ __u32 handle;
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+ __u32 flags;
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+ /** offset into the drm node to use for subsequent mmap call. */
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+ __u64 offset;
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};
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/**
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@@ -201,43 +220,24 @@ struct drm_vc4_create_bo {
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*/
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struct drm_vc4_create_shader_bo {
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/* Size of the data argument. */
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- uint32_t size;
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+ __u32 size;
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/* Flags, currently must be 0. */
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- uint32_t flags;
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+ __u32 flags;
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/* Pointer to the data. */
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- uint64_t data;
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+ __u64 data;
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/** Returned GEM handle for the BO. */
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- uint32_t handle;
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+ __u32 handle;
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/* Pad, must be 0. */
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- uint32_t pad;
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-};
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-
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-/**
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- * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
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- *
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- * This doesn't actually perform an mmap. Instead, it returns the
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- * offset you need to use in an mmap on the DRM device node. This
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- * means that tools like valgrind end up knowing about the mapped
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- * memory.
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- *
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- * There are currently no values for the flags argument, but it may be
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- * used in a future extension.
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- */
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-struct drm_vc4_mmap_bo {
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- /** Handle for the object being mapped. */
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- uint32_t handle;
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- uint32_t flags;
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- /** offset into the drm node to use for subsequent mmap call. */
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- uint64_t offset;
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+ __u32 pad;
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};
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struct drm_vc4_get_hang_state_bo {
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- uint32_t handle;
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- uint32_t paddr;
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- uint32_t size;
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- uint32_t pad;
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+ __u32 handle;
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+ __u32 paddr;
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+ __u32 size;
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+ __u32 pad;
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};
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/**
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@@ -246,34 +246,34 @@ struct drm_vc4_get_hang_state_bo {
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*/
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struct drm_vc4_get_hang_state {
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/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
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- uint64_t bo;
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+ __u64 bo;
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/**
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* On input, the size of the bo array. Output is the number
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* of bos to be returned.
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*/
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- uint32_t bo_count;
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+ __u32 bo_count;
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- uint32_t start_bin, start_render;
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+ __u32 start_bin, start_render;
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- uint32_t ct0ca, ct0ea;
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- uint32_t ct1ca, ct1ea;
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- uint32_t ct0cs, ct1cs;
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- uint32_t ct0ra0, ct1ra0;
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-
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- uint32_t bpca, bpcs;
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- uint32_t bpoa, bpos;
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-
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- uint32_t vpmbase;
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-
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- uint32_t dbge;
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- uint32_t fdbgo;
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- uint32_t fdbgb;
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- uint32_t fdbgr;
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- uint32_t fdbgs;
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- uint32_t errstat;
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+ __u32 ct0ca, ct0ea;
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+ __u32 ct1ca, ct1ea;
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+ __u32 ct0cs, ct1cs;
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+ __u32 ct0ra0, ct1ra0;
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+
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+ __u32 bpca, bpcs;
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+ __u32 bpoa, bpos;
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+
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+ __u32 vpmbase;
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+
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+ __u32 dbge;
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+ __u32 fdbgo;
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+ __u32 fdbgb;
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+ __u32 fdbgr;
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+ __u32 fdbgs;
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+ __u32 errstat;
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/* Pad that we may save more registers into in the future. */
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- uint32_t pad[16];
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+ __u32 pad[16];
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};
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#endif /* _UAPI_VC4_DRM_H_ */
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